Rev |
Log message |
Author |
Age |
Path |
863 |
ORPSoC: Add paramers to or1200-monitor for setting name and path of log files
Two small patches in one to make or1200-monitor more useful outside of orpsocv2:
- Setting log path with a parameter allows more flexible directory layout
- if the plusarg "testcase" is set at runtime, this is used to set a unique
prefix for the log files. Plusargs are currently not used in orpsocv2, so if
it is not set, the name falls back to the value of the parameter
TEST_NAME_STRING. The value of the parameter is set to the define
`TEST_NAME_STRING in the test bench top levele to avoid any changes to the
orpsocv2 scripts. With this, we can get rid of `include test-defines in
or1200_monitor.v
Signed-off-by: Olof Kindgren <olof@opencores.org> |
olof |
3990d 10h |
/openrisc/ |
862 |
sysc: avoid using orpsoc internal classes directly
The problem with using the internal classes directly is
that you have to use the internally generated name,
this in itself is perhaps not such a big issue, the issue
is that the internal name changes when the underlaying verilog
design changes.
This works around this by using the classes through the
top module, which is part of the external api. |
stekern |
4001d 02h |
/openrisc/ |
861 |
sysc: include unistd.h
write, read, pipe et al are declared in this, newer gcc will
warn on missing declerations, thus making the build to fail |
stekern |
4001d 02h |
/openrisc/ |
860 |
or1200_monitor.v: Remove trailing whitespace |
olof |
4005d 07h |
/openrisc/ |
859 |
Execute trapped instruction after breakpoint is removed
Closes bug #104
When the instruction replaced by a trap instruction is restored by the
debugger, this instruction is not executed.
Proposed solution:
- Checked for a debug unstall condition plus a trap condition in
or1200_du(dbg_stall && |except_stop).
- Then, when this event occur, flush the entire pipeline (in or1200_ctrl) and
set the pc to npc in or1200_genpc(which is equal to the trapped instruction
address).
Signed-off-by: Franck Jullien <crevars at opencores.org>
acked-by: Olof Kindgren <olof at opencores.org> |
olof |
4005d 09h |
/openrisc/ |
858 |
orpsoc/tests: Fix or1200-dsxinsn when caches are not present
This test would go into an endless loop when caches are not present. |
stekern |
4105d 15h |
/openrisc/ |
857 |
orpsocv2: remove reference to r32 in context save/restore |
julius |
4115d 05h |
/openrisc/ |
856 |
Fixed rounding of UART divisor |
skrzyp |
4159d 08h |
/openrisc/ |
855 |
Publish OR1K 1.0 architecture spec |
julius |
4202d 07h |
/openrisc/ |
854 |
Add OR1200_OR32_LWS define to board specific or1200_defines.v |
stekern |
4212d 00h |
/openrisc/ |
853 |
Declare pcreg_boot before usage
When things were moved around in rev 813, this error was introduced
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4237d 09h |
/openrisc/ |
852 |
Declare pcreg_boot before usage
When things were moved around in rev 813, this error was introduced
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4237d 09h |
/openrisc/ |
851 |
changed branch delay flags |
skrzyp |
4240d 09h |
/openrisc/ |
850 |
or1200_genpc: fix ipcu_cycstb_o generation
In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).
This fixes this issue.
Patch by: Franck Jullien <franck.jullien@gmail.com> |
stekern |
4252d 01h |
/openrisc/ |
849 |
or1200: Fix for cache bug related to first_{hit|miss}_ack
Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.
Patch by: Matthew Hicks <firefalcon@gmail.com> |
stekern |
4252d 01h |
/openrisc/ |
848 |
or1200: l.lws support
Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.
Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk> |
stekern |
4252d 01h |
/openrisc/ |
847 |
or1200_genpc: fix ipcu_cycstb_o generation
In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).
This fixes this issue.
Patch by: Franck Jullien <franck.jullien@gmail.com> |
stekern |
4252d 01h |
/openrisc/ |
846 |
or1200: Fix for cache bug related to first_{hit|miss}_ack
Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.
Patch by: Matthew Hicks <firefalcon@gmail.com> |
stekern |
4252d 01h |
/openrisc/ |
845 |
or1200: l.lws support
Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.
Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk> |
stekern |
4252d 01h |
/openrisc/ |
844 |
|
skrzyp |
4252d 18h |
/openrisc/ |
843 |
Applied RDiez suggestions |
skrzyp |
4252d 18h |
/openrisc/ |
842 |
Moving GDB 7.1 into the old collection. |
jeremybennett |
4254d 16h |
/openrisc/ |
841 |
GDB 7.2 is now considered the stable version. |
jeremybennett |
4254d 17h |
/openrisc/ |
840 |
Relocate GDB 6.8 to the old directory. |
jeremybennett |
4254d 17h |
/openrisc/ |
839 |
Forgot about updating linker flags, thanks RDiez! |
skrzyp |
4255d 20h |
/openrisc/ |
838 |
added branch-delay option and sets r0 to zero |
skrzyp |
4256d 09h |
/openrisc/ |
837 |
Instructions redirecting users to new directories. |
jeremybennett |
4262d 14h |
/openrisc/ |
836 |
The old legacy directory, which just a README these days. |
jeremybennett |
4262d 15h |
/openrisc/ |
835 |
Move current version to stable directory. |
jeremybennett |
4262d 15h |
/openrisc/ |
834 |
Move current version to stable directory. |
jeremybennett |
4262d 15h |
/openrisc/ |