OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 94

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
94 Finally added byte reading to or_debug_proxy julius 5163d 16h /openrisc/
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5164d 19h /openrisc/
92 Initial version of documents to capture additional information, particularly about the OpenRISC 1200 version 2. jeremybennett 5165d 19h /openrisc/
91 Tidy up of some obsolete configuration code. jeremybennett 5171d 18h /openrisc/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5171d 19h /openrisc/
89 Tidy up for latest bug fixes. jeremybennett 5172d 01h /openrisc/
88 Fix to bug 1710. jeremybennett 5172d 02h /openrisc/
87 Typo fixed. jeremybennett 5172d 02h /openrisc/
86 Bug 1723 fixed (PS2 keyboard error message clarification). jeremybennett 5172d 02h /openrisc/
85 Bug 1773 (RSP usage with ELF image preloaded) fixed. jeremybennett 5172d 03h /openrisc/
84 Remove duplicated directories. jeremybennett 5172d 03h /openrisc/
83 Fix to use -1 to invalidate cache tags. Suggested by John Alfredo. jeremybennett 5172d 17h /openrisc/
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5172d 18h /openrisc/
81 Directory no longer used. jeremybennett 5172d 18h /openrisc/
80 Add missing configuration files to SVN. jeremybennett 5172d 22h /openrisc/
79 Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board julius 5184d 22h /openrisc/
78 Fixed typo in Silos workaround script rherveille 5185d 18h /openrisc/
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5185d 18h /openrisc/
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5186d 18h /openrisc/
75 Fixed toolchain script's cygwin ncurses check julius 5191d 20h /openrisc/
74 Toolchain script fix for ncurses header checking julius 5209d 23h /openrisc/
73 toolchain script error fix julius 5210d 00h /openrisc/
72 Toolchain install script: or1ksim location changed, few tweaks julius 5212d 21h /openrisc/
71 ORPSoC board builds, adding readmes julius 5229d 03h /openrisc/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5233d 08h /openrisc/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5233d 09h /openrisc/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5236d 00h /openrisc/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5236d 03h /openrisc/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5256d 01h /openrisc/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5260d 08h /openrisc/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.