Rev |
Log message |
Author |
Age |
Path |
414 |
Updates to add -mredzone and improved GCC optimizations. |
jeremybennett |
4983d 16h |
/openrisc/ |
413 |
Fixed to combined bug in the assembler and linker. |
jeremybennett |
4984d 19h |
/openrisc/ |
412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
4986d 11h |
/openrisc/ |
411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
4986d 23h |
/openrisc/ |
410 |
ORPSoC: Adding README in root explaining how to build documentation, and
documentation fixup so it builds properly again. |
julius |
4987d 23h |
/openrisc/ |
409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
4987d 23h |
/openrisc/ |
408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4988d 11h |
/openrisc/ |
407 |
Update or1ksim version in toolchain script to rc2 |
julius |
4988d 14h |
/openrisc/ |
406 |
ORPmon indented files, bus, align and instruction errors vectors printf and reboot |
julius |
4988d 14h |
/openrisc/ |
405 |
ORPmon updates - ethernet driver updates |
julius |
4988d 19h |
/openrisc/ |
404 |
New scripts to build separate bare metal and Linux tool chains. Fixes to GDB so it builds with the Linux tool chain and uses RELA. Other minor fixes to the GCC tool chain. |
jeremybennett |
4988d 19h |
/openrisc/ |
403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4989d 17h |
/openrisc/ |
402 |
Further updates to the compiler |
jeremybennett |
4989d 21h |
/openrisc/ |
401 |
Fixing find first one (ff1) and find last one (fl1) support in OR1200.
Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table. |
julius |
4989d 22h |
/openrisc/ |
400 |
Updates to the linker, GCC, newlib and GDB in preparation for supporting C++. The key changes are that the linker now uses RELA and that GCC may save registers at the bottom of the stack before the frame is allocated or after it is deallocated, so exception handlers/thread primitives should not use the first 130 bytes after the SP. |
jeremybennett |
4989d 22h |
/openrisc/ |
399 |
Updates to the linker, GCC, newlib and GDB in preparation for supporting C++. The key changes are that the linker now uses RELA and that GCC may save registers at the bottom of the stack before the frame is allocated or after it is deallocated, so exception handlers/thread primitives should not use the first 130 bytes after the SP. |
jeremybennett |
4990d 00h |
/openrisc/ |
398 |
ORPSoCv2 removing generic backend path - not needed |
julius |
4991d 00h |
/openrisc/ |
397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4991d 22h |
/openrisc/ |
396 |
ORPSoCv2 final software fixes...for now. See updated README |
julius |
4994d 21h |
/openrisc/ |
395 |
ORPSoCv2 moving ethernet tests to correct place |
julius |
4994d 21h |
/openrisc/ |
394 |
ORPSoCv2 removing unused directories |
julius |
4994d 21h |
/openrisc/ |
393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
4994d 21h |
/openrisc/ |
392 |
ORPSoCv2 software path reorganisation stage 1. |
julius |
4995d 13h |
/openrisc/ |
391 |
Removing modules no longer needed in ORPSoCv2 |
julius |
4996d 14h |
/openrisc/ |
390 |
Updated toolchain build scripts to use FTP server on OpenCores.org. |
julius |
4996d 14h |
/openrisc/ |
389 |
SD-Card boot added (sdboot) to the commands in the load file. DOS-filesystem added to support Fat12-16. Driver for SD-card added, SD and SDHC supported
Currently hardcoded to boot from vmlinux.bin |
tac2 |
5006d 22h |
/openrisc/ |
388 |
Tagging the 0.5.0rc2 candidate release of Or1ksim |
jeremybennett |
5019d 21h |
/openrisc/ |
387 |
Fixed testing, to always use our DEJAGNU config. |
jeremybennett |
5019d 21h |
/openrisc/ |
386 |
Updated for release 0.5.0rc2 |
jeremybennett |
5019d 22h |
/openrisc/ |
385 |
Updates for Or1ksim 0.5.0rc2.
* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.
* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected. |
jeremybennett |
5019d 22h |
/openrisc/ |