Rev |
Log message |
Author |
Age |
Path |
504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4868d 13h |
/openrisc/ |
503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4869d 09h |
/openrisc/ |
502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4871d 13h |
/openrisc/ |
501 |
ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default |
julius |
4872d 14h |
/openrisc/ |
500 |
ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc
ML501 simulation makefile update to allow custom ELFs to be specified |
julius |
4872d 17h |
/openrisc/ |
499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4873d 10h |
/openrisc/ |
498 |
or_debug_proxy updates to documentation and Makefile related to latest ftd2xx driver, |
julius |
4874d 22h |
/openrisc/ |
497 |
or_debug_proxy updates |
julius |
4875d 19h |
/openrisc/ |
496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
4875d 20h |
/openrisc/ |
495 |
ORPSoC adding more accessor functions to Micron SDRAM model. |
julius |
4875d 20h |
/openrisc/ |
494 |
Change to ensure handles ctrl-C correctly with empty line. |
jeremybennett |
4886d 14h |
/openrisc/ |
493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
4888d 22h |
/openrisc/ |
492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
4889d 20h |
/openrisc/ |
491 |
ORPSoC or1200_monitor update. |
julius |
4890d 07h |
/openrisc/ |
490 |
Updates to fix spurious test failures and register scheduling. |
jeremybennett |
4894d 13h |
/openrisc/ |
489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
4899d 19h |
/openrisc/ |
488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
4899d 20h |
/openrisc/ |
487 |
ORPSoC main software makefile update |
julius |
4902d 18h |
/openrisc/ |
486 |
ORPSoC updates, mainly software, i2c driver |
julius |
4902d 18h |
/openrisc/ |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4906d 22h |
/openrisc/ |
484 |
Changes to make r12 call-saved and to bring wchar tests in line. |
jeremybennett |
4907d 21h |
/openrisc/ |
483 |
Updated with new opcodes to generate random numbers and to identify us as Or1ksim. |
jeremybennett |
4909d 23h |
/openrisc/ |
482 |
Don't hardcode tool versions in help text |
olof |
4911d 11h |
/openrisc/ |
481 |
OR1200 Update. RTL and spec. |
julius |
4923d 05h |
/openrisc/ |
480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
4924d 03h |
/openrisc/ |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4925d 02h |
/openrisc/ |
478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4926d 18h |
/openrisc/ |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4927d 02h |
/openrisc/ |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4927d 19h |
/openrisc/ |
475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4927d 22h |
/openrisc/ |