| Rev |
Log message |
Author |
Age |
Path |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5332d 23h |
/openrisc/ |
| 56 |
adding generic pll model to orpsoc |
julius |
5341d 01h |
/openrisc/ |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5343d 15h |
/openrisc/ |
| 54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5353d 23h |
/openrisc/ |
| 53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5371d 23h |
/openrisc/ |
| 52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5372d 19h |
/openrisc/ |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5386d 22h |
/openrisc/ |
| 50 |
Adding or32_funcs.S |
julius |
5387d 02h |
/openrisc/ |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5405d 15h |
/openrisc/ |
| 48 |
Adds an initialization to keep GCC happy in jp1_ll_read_jp1. |
jeremybennett |
5405d 18h |
/openrisc/ |
| 47 |
debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions |
julius |
5415d 02h |
/openrisc/ |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5421d 03h |
/openrisc/ |
| 45 |
Orpsoc eth test fix and script error message update |
julius |
5428d 02h |
/openrisc/ |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5457d 02h |
/openrisc/ |
| 43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5480d 23h |
/openrisc/ |
| 42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5496d 20h |
/openrisc/ |
| 41 |
Update to or1k top |
julius |
5499d 21h |
/openrisc/ |
| 40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5501d 03h |
/openrisc/ |
| 39 |
Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update |
julius |
5505d 03h |
/openrisc/ |
| 38 |
Adding binutils, gcc, uClibc patched source and patches |
julius |
5515d 02h |
/openrisc/ |
| 37 |
Update to the toolchain script - uses gcc-core package now instead of complete gcc |
julius |
5515d 03h |
/openrisc/ |
| 36 |
Better clean rule in makefile |
julius |
5515d 03h |
/openrisc/ |
| 35 |
Download and patch files with README files updated to explain what is in the new repository |
jeremybennett |
5515d 21h |
/openrisc/ |
| 34 |
Created directories for download and patch files and added README's explaining what is in each one. |
jeremybennett |
5515d 21h |
/openrisc/ |
| 33 |
version 2.1 of GDB 6.8 for the OpenRISC architecture |
jeremybennett |
5515d 21h |
/openrisc/ |
| 32 |
Tags directory for versions of GDB 6.8 |
jeremybennett |
5515d 21h |
/openrisc/ |
| 31 |
Tags directory for all GDB versions |
jeremybennett |
5515d 21h |
/openrisc/ |
| 30 |
copied rtems from or1k repo |
unneback |
5515d 22h |
/openrisc/ |
| 29 |
|
unneback |
5515d 23h |
/openrisc/ |
| 28 |
|
unneback |
5516d 00h |
/openrisc/ |
