| Rev |
Log message |
Author |
Age |
Path |
| 486 |
Updated with new opcodes to generate random numbers and to identify us as Or1ksim. |
jeremybennett |
4879d 22h |
/openrisc/ |
| 485 |
Use variable names in help text to describe default options |
olof |
4880d 17h |
/openrisc/ |
| 484 |
ORPSoC update - adding ability to use a Modelsim without vopt executable |
julius |
4883d 11h |
/openrisc/ |
| 483 |
ORPSoC OR1200 update. Adding parity testbench and generic fault tolerance testing build. |
julius |
4883d 14h |
/openrisc/ |
| 482 |
ORPSoC updates - adding parity checking RTL, ethernet MAC FIFO buffer updates. Software changes. |
julius |
4888d 08h |
/openrisc/ |
| 481 |
OR1200 Update. RTL and spec. |
julius |
4888d 12h |
/openrisc/ |
| 480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
4889d 10h |
/openrisc/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4890d 09h |
/openrisc/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4892d 01h |
/openrisc/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4892d 09h |
/openrisc/ |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4893d 02h |
/openrisc/ |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4893d 05h |
/openrisc/ |
| 474 |
uC/OS-II port linker flags updated. |
julius |
4893d 11h |
/openrisc/ |
| 473 |
Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. |
jeremybennett |
4894d 05h |
/openrisc/ |
| 472 |
Various changes which improve the quality of the tracing. |
jeremybennett |
4894d 07h |
/openrisc/ |
| 471 |
Adding ucos-ii port. |
julius |
4896d 10h |
/openrisc/ |
| 470 |
ORPSoC OR1200 crt0 updates. |
julius |
4897d 05h |
/openrisc/ |
| 469 |
newlib update - added zeroing of r0 to crt0.S |
julius |
4898d 06h |
/openrisc/ |
| 468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4898d 06h |
/openrisc/ |
| 467 |
ORPmon - bug fixes and clean up. |
julius |
4899d 04h |
/openrisc/ |
| 466 |
ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README |
julius |
4899d 09h |
/openrisc/ |
| 465 |
ORPSoC SPI flash load Makefile and README updates. |
julius |
4900d 00h |
/openrisc/ |
| 464 |
More ORPmon updates. |
julius |
4900d 00h |
/openrisc/ |
| 463 |
ORPmon update |
julius |
4900d 03h |
/openrisc/ |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4900d 08h |
/openrisc/ |
| 461 |
Updated to be much stricter about usage. |
jeremybennett |
4902d 04h |
/openrisc/ |
| 460 |
Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. |
jeremybennett |
4902d 05h |
/openrisc/ |
| 459 |
Add option to bld-all.sh to explicitly set control load of make, and fix typos. |
julius |
4902d 11h |
/openrisc/ |
| 458 |
or1ksim testsuite updates |
julius |
4903d 09h |
/openrisc/ |
| 457 |
or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. |
julius |
4912d 00h |
/openrisc/ |
