Rev |
Log message |
Author |
Age |
Path |
795 |
Created or1200_rel3 branch from rev 794 |
olof |
4481d 18h |
/openrisc/branches/or1200_rel3/ |
794 |
ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file
Fixes lint warnings. |
julius |
4487d 04h |
/openrisc/trunk/or1200/ |
788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4511d 18h |
/openrisc/trunk/or1200/ |
679 |
Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4535d 19h |
/openrisc/trunk/or1200/ |
674 |
or1200: Fix for Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled |
julius |
4578d 03h |
/openrisc/trunk/or1200/ |
647 |
or1200: update documentation to go with recent rtl commits |
julius |
4698d 17h |
/openrisc/trunk/or1200/ |
645 |
or1200: Specification document source now in asciidoc format. ODT and MS Word format documents deprecated, PDF regenerated |
julius |
4716d 17h |
/openrisc/trunk/or1200/ |
644 |
or1200: the infamous l.rfe fix, and bug fix for when multiply is disabled |
julius |
4716d 18h |
/openrisc/trunk/or1200/ |
643 |
or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix |
julius |
4716d 18h |
/openrisc/trunk/or1200/ |
642 |
or1200: add carry, overflow bits, and range exception |
julius |
4716d 18h |
/openrisc/trunk/or1200/ |
641 |
or1200: fix serial multiply/divide bug |
julius |
4716d 18h |
/openrisc/trunk/or1200/ |
640 |
or1200: add l.ext instructions, fix a MAC bug |
julius |
4716d 18h |
/openrisc/trunk/or1200/ |
639 |
or1200: or1200_dpram.v change task set_gpr to function |
julius |
4716d 18h |
/openrisc/trunk/or1200/ |
481 |
OR1200 Update. RTL and spec. |
julius |
4942d 10h |
/openrisc/trunk/or1200/ |
431 |
Updated and move OR1200 supplementary manual.
or_debug_proxy GDB RSP interface fix.
ORPSoC S/W and makefile updates. |
julius |
4998d 20h |
/openrisc/trunk/or1200/ |
401 |
Fixing find first one (ff1) and find last one (fl1) support in OR1200.
Updated documentation, adding missing l.ff1 and l.fl1 opcodes to supported
instructions table. |
julius |
5020d 22h |
/openrisc/trunk/or1200/ |
364 |
OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.
OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)
OR1200 spec updated to version 0.9, various updates.
OR1200 in ORPSoC and main OR1200 in sync, only difference is defines. |
julius |
5070d 19h |
/openrisc/trunk/or1200/ |
359 |
Removing duplicate OR1200 spec from docs/ path, original in or1200/doc should be used instead, also moving Japanese OR1200 spec to or1200/doc |
julius |
5073d 01h |
/openrisc/trunk/or1200/ |
358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5073d 04h |
/openrisc/trunk/or1200/ |
356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5073d 13h |
/openrisc/trunk/or1200/ |
353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5074d 21h |
/openrisc/trunk/or1200/ |
352 |
OR1200 RTL DC sensitivity list fix |
julius |
5075d 19h |
/openrisc/trunk/or1200/ |
260 |
Fixed `define in FPU that didnt need to be there |
julius |
5081d 17h |
/openrisc/trunk/or1200/ |
259 |
Fixing or1200_defines FPU module selection defines - They are no longer needed |
julius |
5083d 13h |
/openrisc/trunk/or1200/ |
258 |
Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off |
julius |
5083d 13h |
/openrisc/trunk/or1200/ |
187 |
Or1200 sprs FPU update |
julius |
5133d 17h |
/openrisc/trunk/or1200/ |
186 |
OR1200 RTL FPU fix - RF writeback signal working properly again |
julius |
5133d 20h |
/openrisc/trunk/or1200/ |
185 |
Adding single precision FPU to or1200, initial checkin, not fully tested yet |
julius |
5133d 21h |
/openrisc/trunk/or1200/ |
151 |
OR1200 rel3 (added some files that were not checked-in earlier) |
marcus.erlandsson |
5142d 17h |
/openrisc/trunk/or1200/ |
142 |
added OpenRISC version rel3 |
marcus.erlandsson |
5145d 01h |
/openrisc/trunk/or1200/ |