OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.4.0/] [doc/] - Rev 127

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
127 New config option to allow l.xori with unsigned operand. jeremybennett 5171d 11h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
124 Overflow handling now in line with architecture manual. Tests added. jeremybennett 5172d 07h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
123 Implementation of l.mfspr and l.mtspr corrected to use bitwise OR rather than addition. Associated tests added. jeremybennett 5172d 11h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5173d 08h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5174d 05h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5176d 08h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5178d 07h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
110 or1ksim make check should work without a libc in the or32-elf tools julius 5179d 09h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5181d 08h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
104 Candidate release 0.4.0rc4 jeremybennett 5184d 15h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5193d 09h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
100 Single precision FPU stuff for or1ksim julius 5193d 11h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
99 Bug in test evaluation for library fixed. jeremybennett 5198d 09h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5199d 11h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5213d 17h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5214d 18h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5220d 08h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
91 Tidy up of some obsolete configuration code. jeremybennett 5227d 07h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5227d 08h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
85 Bug 1773 (RSP usage with ELF image preloaded) fixed. jeremybennett 5227d 16h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
82 Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check".

Incorporate Mark Jarvis's fixes for Mac OS X.		 jeremybennett 5228d 07h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
80 Add missing configuration files to SVN. jeremybennett 5228d 11h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/
19 Initial commit of Or1ksim 0.3.0 into the new repository jeremybennett 5558d 17h /openrisc/tags/or1ksim/or1ksim-0.4.0/doc/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.