OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 362

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 5037d 00h /openrisc/trunk/
361 OPRSoCv2 - adding things left out in last check-in julius 5037d 05h /openrisc/trunk/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5037d 05h /openrisc/trunk/
359 Removing duplicate OR1200 spec from docs/ path, original in or1200/doc should be used instead, also moving Japanese OR1200 spec to or1200/doc julius 5037d 12h /openrisc/trunk/
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.
julius 5037d 14h /openrisc/trunk/
357 Tidied up commenting. jeremybennett 5037d 15h /openrisc/trunk/
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests
julius 5037d 23h /openrisc/trunk/
355 Adding CoreMark to ORPmon, updated Dhrystone test output julius 5038d 07h /openrisc/trunk/
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.
julius 5039d 05h /openrisc/trunk/
353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.
julius 5039d 07h /openrisc/trunk/
352 OR1200 RTL DC sensitivity list fix julius 5040d 05h /openrisc/trunk/
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5040d 05h /openrisc/trunk/
350 Adding new OR1200 processor to ORPSoCv2 julius 5040d 09h /openrisc/trunk/
349 ORPSoCv2 update with new software and makefile update julius 5040d 09h /openrisc/trunk/
348 First stage of ORPSoCv2 update - more to come julius 5040d 10h /openrisc/trunk/
346 Changes to support Or1ksim 0.5.0rc1

Top level changes:

* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.

Changes in testsuite:

* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.

Changes in testsuite/test-code-or1k:

* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.
jeremybennett 5040d 11h /openrisc/trunk/
343 Build C++ and its libraries. jeremybennett 5041d 08h /openrisc/trunk/
342 Various files regenerated as part of RC1 creation. jeremybennett 5041d 08h /openrisc/trunk/
339 Updates for GDB 7.2 for OpenRISC version 1.0 release candidate 1. OpenRISC
documentation subsumes the old separate OpenRISC document.
jeremybennett 5041d 13h /openrisc/trunk/
336 Corrected for 4.5.1-or32-1.0rc1 jeremybennett 5042d 06h /openrisc/trunk/
335 Updated version number to 4.5.1-or32-1.0. jeremybennett 5042d 06h /openrisc/trunk/
334 Record changes to the documentation and option handling. jeremybennett 5042d 06h /openrisc/trunk/
333 Fix the default option (to use -mhard-mul). Update the documentation for
OpenRISC.
jeremybennett 5042d 06h /openrisc/trunk/
332 Provide support for nested functions. Tidy up board specification.

* config/or32/or32-protos.c <or32_trampoline_code_size>: Added.
* config/or32/or32.c <OR32_MOVHI, OR32_ORI, OR32_LWZ, OR32_JR>:
New macros added.
(or32_emit_mode, or32_emit_binary, or32_force_binary)
(or32_trampoline_code_size, or32_trampoline_init): Created.
(or32_output_bf): Tabbing fixed.
<TARGET_TRAMPOLINE_INIT>: Definition added.
* config/or32/or32.h <STATIC_CHAIN_REGNUM>: Uses R11.
<TRAMPOLINE_SIZE>: redefined.
<TRAMPOLINE_ENVIRONMENT>: Added definition.
jeremybennett 5043d 05h /openrisc/trunk/
331 Updated for GDB 7.2 and GCC 4.5.1 (which needs target-libgcc). jeremybennett 5043d 14h /openrisc/trunk/
330 Baseline port of GDB 7.2 for OpenRISC 1000 jeremybennett 5044d 00h /openrisc/trunk/
329 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5044d 01h /openrisc/trunk/
328 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5044d 01h /openrisc/trunk/
327 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5044d 01h /openrisc/trunk/
326 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5044d 01h /openrisc/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.