| Rev |
Log message |
Author |
Age |
Path |
| 381 |
Crossbuild script for 1.0 updated to use new GCC rc2 patch and linux-2.6.35 |
julius |
4984d 03h |
/openrisc/trunk/ |
| 380 |
Adding new Linux-2.6.35 patch, to be built with new 1.0 toolchain |
julius |
4984d 03h |
/openrisc/trunk/ |
| 379 |
Linux-2.6.34 patch update - ethernet stability fix and USB host (ohs900) startup device detect improvement |
julius |
4984d 04h |
/openrisc/trunk/ |
| 378 |
Adding gcc-4.5.1 patches to enable kernel to build again |
julius |
4984d 08h |
/openrisc/trunk/ |
| 377 |
gcc-4.5.1/gcc/config/or32/or32.c:
Swap INTVAL for REGNO in or32_legitimate_address_p fixing 64-bit
machine build errors. |
julius |
4984d 23h |
/openrisc/trunk/ |
| 376 |
Adding handling cases for RSP queries seen from new gdb-7.2 in RSP servers in
or1ksim and or_debug_proxy.
Adding ChangeLog to or_debug_proxy |
julius |
4989d 10h |
/openrisc/trunk/ |
| 375 |
ORPmon update for compatibility with OR toolchain 1.0rc1 |
julius |
4990d 04h |
/openrisc/trunk/ |
| 374 |
ORPSoCv2 adding some files forgotten from last checkin |
julius |
4990d 04h |
/openrisc/trunk/ |
| 373 |
ORPSoCv2 software update for compatibility with OR toolchain 1.0 |
julius |
4990d 04h |
/openrisc/trunk/ |
| 372 |
Toolchain install script uClibc variable update |
julius |
4990d 07h |
/openrisc/trunk/ |
| 371 |
Toolchain install script binutils commented out fix |
julius |
4990d 07h |
/openrisc/trunk/ |
| 370 |
Toolchain install script uclibc url fix |
julius |
4990d 07h |
/openrisc/trunk/ |
| 369 |
Toolchain build script binutils path fix |
julius |
4990d 08h |
/openrisc/trunk/ |
| 368 |
Toolchain script: adding sim url path |
julius |
4990d 08h |
/openrisc/trunk/ |
| 367 |
Fixup 1.0 release script |
julius |
4990d 08h |
/openrisc/trunk/ |
| 366 |
Version 1.0 toolchain script commit |
julius |
4990d 08h |
/openrisc/trunk/ |
| 365 |
Linux-2.6.34 patch update with updated USB ohs900 host |
julius |
4993d 02h |
/openrisc/trunk/ |
| 364 |
OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.
OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)
OR1200 spec updated to version 0.9, various updates.
OR1200 in ORPSoC and main OR1200 in sync, only difference is defines. |
julius |
5002d 01h |
/openrisc/trunk/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5002d 11h |
/openrisc/trunk/ |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5003d 21h |
/openrisc/trunk/ |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5004d 01h |
/openrisc/trunk/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5004d 01h |
/openrisc/trunk/ |
| 359 |
Removing duplicate OR1200 spec from docs/ path, original in or1200/doc should be used instead, also moving Japanese OR1200 spec to or1200/doc |
julius |
5004d 08h |
/openrisc/trunk/ |
| 358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5004d 10h |
/openrisc/trunk/ |
| 357 |
Tidied up commenting. |
jeremybennett |
5004d 11h |
/openrisc/trunk/ |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5004d 20h |
/openrisc/trunk/ |
| 355 |
Adding CoreMark to ORPmon, updated Dhrystone test output |
julius |
5005d 03h |
/openrisc/trunk/ |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5006d 01h |
/openrisc/trunk/ |
| 353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5006d 04h |
/openrisc/trunk/ |
| 352 |
OR1200 RTL DC sensitivity list fix |
julius |
5007d 01h |
/openrisc/trunk/ |
