OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 443

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
443 Work in progress on more efficient Ethernet. jeremybennett 4946d 21h /openrisc/trunk/
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4947d 11h /openrisc/trunk/
441 Changes for gdbserver. jeremybennett 4947d 17h /openrisc/trunk/
440 Updated documentation to describe new Ethernet usage. jeremybennett 4948d 12h /openrisc/trunk/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4950d 17h /openrisc/trunk/
438 Fix to newlib header and library locations. jeremybennett 4953d 17h /openrisc/trunk/
437 Or1ksim - ethernet peripheral update, working much better. julius 4956d 07h /openrisc/trunk/
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4957d 07h /openrisc/trunk/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4957d 08h /openrisc/trunk/
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4960d 13h /openrisc/trunk/
433 New single program interrupt test programs. jeremybennett 4961d 15h /openrisc/trunk/
432 Updates to handle interrupts correctly. jeremybennett 4961d 16h /openrisc/trunk/
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.		 julius 4963d 15h /openrisc/trunk/
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 4964d 13h /openrisc/trunk/
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.		 julius 4964d 17h /openrisc/trunk/
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4967d 12h /openrisc/trunk/
427 Fixes for C++ to correspond to fixes in uClibc. jeremybennett 4968d 21h /openrisc/trunk/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4970d 07h /openrisc/trunk/
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4970d 08h /openrisc/trunk/
424 C++ library, needed for C++ compiler. jeremybennett 4970d 18h /openrisc/trunk/
423 Minor typo fixed. jeremybennett 4970d 21h /openrisc/trunk/
422 Separates out --force actions, so only build dirs corresponding to targets being built are blown away. jeremybennett 4970d 21h /openrisc/trunk/
421 Fixing some typos in bld-all.sh's --help printout and changed all
"cd .." lines to "cd -".		 julius 4973d 19h /openrisc/trunk/
420 New feature to trace instructions (option --trace). Manual updated to match. jeremybennett 4975d 17h /openrisc/trunk/
419 ORPmon: Fixed interrupt routines in reset.S so they are compatible with new
GCC port (skip over redzone).
Added some defines to easily switch what is done when an error vector
is executed.
Added ability to print out EPCR when crashing.
Changed linker script back to one which doesn't skip over holes in SPI
flash memories.		 julius 4975d 20h /openrisc/trunk/
418 Or1ksim - adding new option when configuring memories, "exitnops" julius 4975d 20h /openrisc/trunk/
417 ORPSoC re-adding doc automake files, this time not symlinks julius 4978d 17h /openrisc/trunk/
416 ORPSoC doc cleanup - removing symlinks from automake'd docs build path julius 4978d 17h /openrisc/trunk/
415 ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.		 julius 4978d 17h /openrisc/trunk/
414 Updates to add -mredzone and improved GCC optimizations. jeremybennett 4979d 12h /openrisc/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.