URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 455

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
455	Updated to support threads. Does require thread debugging enabled in uClibc.	jeremybennett	4927d 01h	/openrisc/trunk/
454	Updated to incorporate pthreads for Linux tool chain.	jeremybennett	4929d 03h	/openrisc/trunk/
453	Updates to support constructor/destructor initialization for uClibc.	jeremybennett	4929d 14h	/openrisc/trunk/
452	Update to define __UCLIBC__ when using the uClibc tool chain.	jeremybennett	4929d 22h	/openrisc/trunk/
451	More tidying up.	jeremybennett	4933d 18h	/openrisc/trunk/
450	Simplified (and hopefully more reliable) Ethernet MAC/PHY.	jeremybennett	4933d 22h	/openrisc/trunk/
449	ORPSoC - or1200_monitor.v additions enabling new experimental execution checks. Replace use of "clean-all" with "distclean" as make rule to clean things.	julius	4935d 18h	/openrisc/trunk/
448	Changed or32 to openrisc as Linux architecture name.	jeremybennett	4936d 04h	/openrisc/trunk/
447	Updates to register order.	jeremybennett	4936d 22h	/openrisc/trunk/
446	gdb-7.2 gdbserver updates.	julius	4937d 17h	/openrisc/trunk/
445	gdbserver update to use kernel port ptrace register definitions.	julius	4938d 14h	/openrisc/trunk/
444	Changes to ABI handling of varargs.	jeremybennett	4938d 22h	/openrisc/trunk/
443	Work in progress on more efficient Ethernet.	jeremybennett	4939d 02h	/openrisc/trunk/
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	4939d 16h	/openrisc/trunk/
441	Changes for gdbserver.	jeremybennett	4939d 23h	/openrisc/trunk/
440	Updated documentation to describe new Ethernet usage.	jeremybennett	4940d 18h	/openrisc/trunk/
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4942d 22h	/openrisc/trunk/
438	Fix to newlib header and library locations.	jeremybennett	4945d 22h	/openrisc/trunk/
437	Or1ksim - ethernet peripheral update, working much better.	julius	4948d 12h	/openrisc/trunk/
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	4949d 13h	/openrisc/trunk/
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	4949d 13h	/openrisc/trunk/
434	Work in progress with new Ethernet TUN/TAP interface.	jeremybennett	4952d 19h	/openrisc/trunk/
433	New single program interrupt test programs.	jeremybennett	4953d 21h	/openrisc/trunk/
432	Updates to handle interrupts correctly.	jeremybennett	4953d 22h	/openrisc/trunk/
431	Updated and move OR1200 supplementary manual. or_debug_proxy GDB RSP interface fix. ORPSoC S/W and makefile updates.	julius	4955d 21h	/openrisc/trunk/
430	or1ksim - clarifying interrupt behavior in code and documentation.	julius	4956d 19h	/openrisc/trunk/
429	or1ksim update - remove debug printfs from eth MDIO emulation function and fix illegal instruction vector jump for invalid instructions.	julius	4956d 22h	/openrisc/trunk/
428	or1ksim - adding preliminary PHY emulation to ethernet peripheral.	julius	4959d 18h	/openrisc/trunk/
427	Fixes for C++ to correspond to fixes in uClibc.	jeremybennett	4961d 02h	/openrisc/trunk/
426	ORPSoC update Reverted back to previous OR1200 instruction cache. (...which...) Fixed or1200-except test failure on generic model. ML501 build not passing or1200-except test. Tried disabling burst on the bus (memory server doesn't support it yet) to no avail. To be continued...	julius	4962d 13h	/openrisc/trunk/

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 455

Filtering Options