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Rev Log message Author Age Path
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4897d 23h /openrisc/trunk/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4898d 22h /openrisc/trunk/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4900d 14h /openrisc/trunk/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.
julius 4900d 22h /openrisc/trunk/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4901d 15h /openrisc/trunk/
475 ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. julius 4901d 18h /openrisc/trunk/
474 uC/OS-II port linker flags updated. julius 4902d 00h /openrisc/trunk/
473 Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. jeremybennett 4902d 18h /openrisc/trunk/
472 Various changes which improve the quality of the tracing. jeremybennett 4902d 20h /openrisc/trunk/
471 Adding ucos-ii port. julius 4904d 23h /openrisc/trunk/
470 ORPSoC OR1200 crt0 updates. julius 4905d 18h /openrisc/trunk/
469 newlib update - added zeroing of r0 to crt0.S julius 4906d 19h /openrisc/trunk/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 4906d 19h /openrisc/trunk/
467 ORPmon - bug fixes and clean up. julius 4907d 16h /openrisc/trunk/
466 ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README
julius 4907d 22h /openrisc/trunk/
465 ORPSoC SPI flash load Makefile and README updates. julius 4908d 12h /openrisc/trunk/
464 More ORPmon updates. julius 4908d 13h /openrisc/trunk/
463 ORPmon update julius 4908d 16h /openrisc/trunk/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.
julius 4908d 21h /openrisc/trunk/
461 Updated to be much stricter about usage. jeremybennett 4910d 17h /openrisc/trunk/
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4910d 18h /openrisc/trunk/
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 4911d 00h /openrisc/trunk/
458 or1ksim testsuite updates julius 4911d 22h /openrisc/trunk/
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4920d 12h /openrisc/trunk/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4920d 14h /openrisc/trunk/
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4924d 16h /openrisc/trunk/
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4926d 18h /openrisc/trunk/
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4927d 04h /openrisc/trunk/
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4927d 13h /openrisc/trunk/
451 More tidying up. jeremybennett 4931d 08h /openrisc/trunk/

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