OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 529

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
529 or_debug_proxy updates julius 4802d 17h /openrisc/trunk/
528 ORPSoC SPI flash programming link script bug fix julius 4804d 03h /openrisc/trunk/
527 newlib-1.18.0 port update, name of support library header now or1k-support.h julius 4804d 17h /openrisc/trunk/
526 uC/OS-II port fix for user interrupt handler julius 4805d 01h /openrisc/trunk/
525 uC/OS-II port fix: account for redzone during task stack initialisation julius 4805d 01h /openrisc/trunk/
524 Various tidy ups to GDB and updates to the simulation boards for the latest GCC. jeremybennett 4809d 20h /openrisc/trunk/
523 Changes to -mnewlib is no longer needed with the or32-elf tool chain. jeremybennett 4810d 23h /openrisc/trunk/
522 Miscellaneous tidy ups. jeremybennett 4812d 03h /openrisc/trunk/
518 Missing parts of checkin from revision 515. Version now 1.0rc4. julius 4814d 21h /openrisc/trunk/
517 newlib updates with or1k support functions, libgloss cleanup julius 4815d 14h /openrisc/trunk/
515 Minor synch with recent changes by Joern. jeremybennett 4815d 21h /openrisc/trunk/
514 Changes for version 1.0rc3 for OpenRISC 1000. Various bugs and tests fixed. jeremybennett 4816d 00h /openrisc/trunk/
512 Updates for release 1.0rc3 for the OpenRISC 1000. jeremybennett 4816d 03h /openrisc/trunk/
510 Updates for release 0.5.1rc1. jeremybennett 4817d 02h /openrisc/trunk/
508 Updates for Or1ksim 0.5.0rc3. jeremybennett 4818d 02h /openrisc/trunk/
507 Newlib libgloss board support update. Corresponding GCC port changes to support it. julius 4823d 22h /openrisc/trunk/
506 ORPSoC or1200 interrupt and syscall generation test julius 4824d 22h /openrisc/trunk/
505 OR1200 overflow detection fixup

SPIflash program update

or1200 driver library timer improvement
julius 4824d 22h /openrisc/trunk/
504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4841d 18h /openrisc/trunk/
503 ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. julius 4842d 14h /openrisc/trunk/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default
julius 4844d 18h /openrisc/trunk/
501 ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default
julius 4845d 19h /openrisc/trunk/
500 ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc

ML501 simulation makefile update to allow custom ELFs to be specified
julius 4845d 22h /openrisc/trunk/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4846d 15h /openrisc/trunk/
498 or_debug_proxy updates to documentation and Makefile related to latest ftd2xx driver, julius 4848d 03h /openrisc/trunk/
497 or_debug_proxy updates julius 4849d 00h /openrisc/trunk/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4849d 01h /openrisc/trunk/
495 ORPSoC adding more accessor functions to Micron SDRAM model. julius 4849d 01h /openrisc/trunk/
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 4859d 19h /openrisc/trunk/
493 ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. julius 4862d 03h /openrisc/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.