OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 60

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5296d 20h /openrisc/trunk/
59 Toolchain install script gcc patch change and gdb configure change julius 5317d 20h /openrisc/trunk/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5320d 19h /openrisc/trunk/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5325d 23h /openrisc/trunk/
56 adding generic pll model to orpsoc julius 5334d 01h /openrisc/trunk/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5336d 15h /openrisc/trunk/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5346d 22h /openrisc/trunk/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5364d 23h /openrisc/trunk/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5365d 19h /openrisc/trunk/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5379d 21h /openrisc/trunk/
50 Adding or32_funcs.S julius 5380d 02h /openrisc/trunk/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5398d 15h /openrisc/trunk/
48 Adds an initialization to keep GCC happy in jp1_ll_read_jp1. jeremybennett 5398d 18h /openrisc/trunk/
47 debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions julius 5408d 02h /openrisc/trunk/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5414d 03h /openrisc/trunk/
45 Orpsoc eth test fix and script error message update julius 5421d 02h /openrisc/trunk/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5450d 02h /openrisc/trunk/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5473d 23h /openrisc/trunk/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5489d 20h /openrisc/trunk/
41 Update to or1k top julius 5492d 21h /openrisc/trunk/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5494d 02h /openrisc/trunk/
39 Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update julius 5498d 03h /openrisc/trunk/
38 Adding binutils, gcc, uClibc patched source and patches julius 5508d 02h /openrisc/trunk/
37 Update to the toolchain script - uses gcc-core package now instead of complete gcc julius 5508d 03h /openrisc/trunk/
36 Better clean rule in makefile julius 5508d 03h /openrisc/trunk/
35 Download and patch files with README files updated to explain what is in the new repository jeremybennett 5508d 20h /openrisc/trunk/
34 Created directories for download and patch files and added README's explaining what is in each one. jeremybennett 5508d 21h /openrisc/trunk/
30 copied rtems from or1k repo unneback 5508d 22h /openrisc/trunk/
29 unneback 5508d 23h /openrisc/trunk/
28 unneback 5509d 00h /openrisc/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.