Rev |
Log message |
Author |
Age |
Path |
862 |
sysc: avoid using orpsoc internal classes directly
The problem with using the internal classes directly is
that you have to use the internally generated name,
this in itself is perhaps not such a big issue, the issue
is that the internal name changes when the underlaying verilog
design changes.
This works around this by using the classes through the
top module, which is part of the external api. |
stekern |
4002d 13h |
/openrisc/trunk/ |
861 |
sysc: include unistd.h
write, read, pipe et al are declared in this, newer gcc will
warn on missing declerations, thus making the build to fail |
stekern |
4002d 13h |
/openrisc/trunk/ |
860 |
or1200_monitor.v: Remove trailing whitespace |
olof |
4006d 19h |
/openrisc/trunk/ |
859 |
Execute trapped instruction after breakpoint is removed
Closes bug #104
When the instruction replaced by a trap instruction is restored by the
debugger, this instruction is not executed.
Proposed solution:
- Checked for a debug unstall condition plus a trap condition in
or1200_du(dbg_stall && |except_stop).
- Then, when this event occur, flush the entire pipeline (in or1200_ctrl) and
set the pc to npc in or1200_genpc(which is equal to the trapped instruction
address).
Signed-off-by: Franck Jullien <crevars at opencores.org>
acked-by: Olof Kindgren <olof at opencores.org> |
olof |
4006d 20h |
/openrisc/trunk/ |
858 |
orpsoc/tests: Fix or1200-dsxinsn when caches are not present
This test would go into an endless loop when caches are not present. |
stekern |
4107d 02h |
/openrisc/trunk/ |
857 |
orpsocv2: remove reference to r32 in context save/restore |
julius |
4116d 16h |
/openrisc/trunk/ |
856 |
Fixed rounding of UART divisor |
skrzyp |
4160d 19h |
/openrisc/trunk/ |
855 |
Publish OR1K 1.0 architecture spec |
julius |
4203d 18h |
/openrisc/trunk/ |
854 |
Add OR1200_OR32_LWS define to board specific or1200_defines.v |
stekern |
4213d 12h |
/openrisc/trunk/ |
853 |
Declare pcreg_boot before usage
When things were moved around in rev 813, this error was introduced
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4238d 21h |
/openrisc/trunk/ |
852 |
Declare pcreg_boot before usage
When things were moved around in rev 813, this error was introduced
Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org> |
olof |
4238d 21h |
/openrisc/trunk/ |
851 |
changed branch delay flags |
skrzyp |
4241d 20h |
/openrisc/trunk/ |
850 |
or1200_genpc: fix ipcu_cycstb_o generation
In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).
This fixes this issue.
Patch by: Franck Jullien <franck.jullien@gmail.com> |
stekern |
4253d 13h |
/openrisc/trunk/ |
849 |
or1200: Fix for cache bug related to first_{hit|miss}_ack
Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.
Patch by: Matthew Hicks <firefalcon@gmail.com> |
stekern |
4253d 13h |
/openrisc/trunk/ |
848 |
or1200: l.lws support
Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.
Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk> |
stekern |
4253d 13h |
/openrisc/trunk/ |
847 |
or1200_genpc: fix ipcu_cycstb_o generation
In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).
This fixes this issue.
Patch by: Franck Jullien <franck.jullien@gmail.com> |
stekern |
4253d 13h |
/openrisc/trunk/ |
846 |
or1200: Fix for cache bug related to first_{hit|miss}_ack
Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.
Patch by: Matthew Hicks <firefalcon@gmail.com> |
stekern |
4253d 13h |
/openrisc/trunk/ |
845 |
or1200: l.lws support
Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.
Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk> |
stekern |
4253d 13h |
/openrisc/trunk/ |
844 |
|
skrzyp |
4254d 06h |
/openrisc/trunk/ |
843 |
Applied RDiez suggestions |
skrzyp |
4254d 06h |
/openrisc/trunk/ |
842 |
Moving GDB 7.1 into the old collection. |
jeremybennett |
4256d 04h |
/openrisc/trunk/ |
841 |
GDB 7.2 is now considered the stable version. |
jeremybennett |
4256d 04h |
/openrisc/trunk/ |
840 |
Relocate GDB 6.8 to the old directory. |
jeremybennett |
4256d 04h |
/openrisc/trunk/ |
839 |
Forgot about updating linker flags, thanks RDiez! |
skrzyp |
4257d 07h |
/openrisc/trunk/ |
838 |
added branch-delay option and sets r0 to zero |
skrzyp |
4257d 21h |
/openrisc/trunk/ |
837 |
Instructions redirecting users to new directories. |
jeremybennett |
4264d 02h |
/openrisc/trunk/ |
836 |
The old legacy directory, which just a README these days. |
jeremybennett |
4264d 02h |
/openrisc/trunk/ |
835 |
Move current version to stable directory. |
jeremybennett |
4264d 02h |
/openrisc/trunk/ |
834 |
Move current version to stable directory. |
jeremybennett |
4264d 02h |
/openrisc/trunk/ |
833 |
Move current version to stable directory. |
jeremybennett |
4264d 02h |
/openrisc/trunk/ |