OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] - Rev 471

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
471 Adding ucos-ii port. julius 4915d 03h /openrisc/trunk/
470 ORPSoC OR1200 crt0 updates. julius 4915d 22h /openrisc/trunk/
469 newlib update - added zeroing of r0 to crt0.S julius 4916d 23h /openrisc/trunk/
468 ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI
julius 4917d 00h /openrisc/trunk/
467 ORPmon - bug fixes and clean up. julius 4917d 21h /openrisc/trunk/
466 ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README
julius 4918d 03h /openrisc/trunk/
465 ORPSoC SPI flash load Makefile and README updates. julius 4918d 17h /openrisc/trunk/
464 More ORPmon updates. julius 4918d 18h /openrisc/trunk/
463 ORPmon update julius 4918d 20h /openrisc/trunk/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.
julius 4919d 02h /openrisc/trunk/
461 Updated to be much stricter about usage. jeremybennett 4920d 21h /openrisc/trunk/
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4920d 22h /openrisc/trunk/
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 4921d 04h /openrisc/trunk/
458 or1ksim testsuite updates julius 4922d 03h /openrisc/trunk/
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4930d 17h /openrisc/trunk/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4930d 18h /openrisc/trunk/
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4934d 20h /openrisc/trunk/
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4936d 22h /openrisc/trunk/
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4937d 09h /openrisc/trunk/
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4937d 17h /openrisc/trunk/
451 More tidying up. jeremybennett 4941d 13h /openrisc/trunk/
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4941d 17h /openrisc/trunk/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 4943d 13h /openrisc/trunk/
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 4943d 23h /openrisc/trunk/
447 Updates to register order. jeremybennett 4944d 17h /openrisc/trunk/
446 gdb-7.2 gdbserver updates. julius 4945d 12h /openrisc/trunk/
445 gdbserver update to use kernel port ptrace register definitions. julius 4946d 09h /openrisc/trunk/
444 Changes to ABI handling of varargs. jeremybennett 4946d 17h /openrisc/trunk/
443 Work in progress on more efficient Ethernet. jeremybennett 4946d 21h /openrisc/trunk/
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4947d 11h /openrisc/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.