Rev |
Log message |
Author |
Age |
Path |
439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4950d 15h |
/openrisc/trunk/orpsocv2/ |
435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4957d 06h |
/openrisc/trunk/orpsocv2/ |
431 |
Updated and move OR1200 supplementary manual.
or_debug_proxy GDB RSP interface fix.
ORPSoC S/W and makefile updates. |
julius |
4963d 14h |
/openrisc/trunk/orpsocv2/ |
426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
4970d 05h |
/openrisc/trunk/orpsocv2/ |
425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4970d 06h |
/openrisc/trunk/orpsocv2/ |
417 |
ORPSoC re-adding doc automake files, this time not symlinks |
julius |
4978d 15h |
/openrisc/trunk/orpsocv2/ |
416 |
ORPSoC doc cleanup - removing symlinks from automake'd docs build path |
julius |
4978d 15h |
/openrisc/trunk/orpsocv2/ |
415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4978d 15h |
/openrisc/trunk/orpsocv2/ |
412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
4982d 05h |
/openrisc/trunk/orpsocv2/ |
411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
4982d 17h |
/openrisc/trunk/orpsocv2/ |
410 |
ORPSoC: Adding README in root explaining how to build documentation, and
documentation fixup so it builds properly again. |
julius |
4983d 17h |
/openrisc/trunk/orpsocv2/ |
409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
4983d 17h |
/openrisc/trunk/orpsocv2/ |
408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4984d 05h |
/openrisc/trunk/orpsocv2/ |
403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4985d 11h |
/openrisc/trunk/orpsocv2/ |
398 |
ORPSoCv2 removing generic backend path - not needed |
julius |
4986d 18h |
/openrisc/trunk/orpsocv2/ |
397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4987d 16h |
/openrisc/trunk/orpsocv2/ |
396 |
ORPSoCv2 final software fixes...for now. See updated README |
julius |
4990d 15h |
/openrisc/trunk/orpsocv2/ |
395 |
ORPSoCv2 moving ethernet tests to correct place |
julius |
4990d 16h |
/openrisc/trunk/orpsocv2/ |
394 |
ORPSoCv2 removing unused directories |
julius |
4990d 16h |
/openrisc/trunk/orpsocv2/ |
393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
4990d 16h |
/openrisc/trunk/orpsocv2/ |
392 |
ORPSoCv2 software path reorganisation stage 1. |
julius |
4991d 08h |
/openrisc/trunk/orpsocv2/ |
391 |
Removing modules no longer needed in ORPSoCv2 |
julius |
4992d 08h |
/openrisc/trunk/orpsocv2/ |
374 |
ORPSoCv2 adding some files forgotten from last checkin |
julius |
5023d 15h |
/openrisc/trunk/orpsocv2/ |
373 |
ORPSoCv2 software update for compatibility with OR toolchain 1.0 |
julius |
5023d 15h |
/openrisc/trunk/orpsocv2/ |
364 |
OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.
OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)
OR1200 spec updated to version 0.9, various updates.
OR1200 in ORPSoC and main OR1200 in sync, only difference is defines. |
julius |
5035d 12h |
/openrisc/trunk/orpsocv2/ |
363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5035d 22h |
/openrisc/trunk/orpsocv2/ |
362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5037d 07h |
/openrisc/trunk/orpsocv2/ |
361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5037d 12h |
/openrisc/trunk/orpsocv2/ |
360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5037d 12h |
/openrisc/trunk/orpsocv2/ |
358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5037d 21h |
/openrisc/trunk/orpsocv2/ |