Rev |
Log message |
Author |
Age |
Path |
504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4834d 11h |
/openrisc/trunk/orpsocv2/ |
503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4835d 07h |
/openrisc/trunk/orpsocv2/ |
502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4837d 11h |
/openrisc/trunk/orpsocv2/ |
501 |
ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default |
julius |
4838d 11h |
/openrisc/trunk/orpsocv2/ |
500 |
ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc
ML501 simulation makefile update to allow custom ELFs to be specified |
julius |
4838d 14h |
/openrisc/trunk/orpsocv2/ |
499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4839d 07h |
/openrisc/trunk/orpsocv2/ |
496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
4841d 18h |
/openrisc/trunk/orpsocv2/ |
495 |
ORPSoC adding more accessor functions to Micron SDRAM model. |
julius |
4841d 18h |
/openrisc/trunk/orpsocv2/ |
493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
4854d 20h |
/openrisc/trunk/orpsocv2/ |
492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
4855d 18h |
/openrisc/trunk/orpsocv2/ |
491 |
ORPSoC or1200_monitor update. |
julius |
4856d 05h |
/openrisc/trunk/orpsocv2/ |
489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
4865d 17h |
/openrisc/trunk/orpsocv2/ |
488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
4865d 18h |
/openrisc/trunk/orpsocv2/ |
487 |
ORPSoC main software makefile update |
julius |
4868d 15h |
/openrisc/trunk/orpsocv2/ |
486 |
ORPSoC updates, mainly software, i2c driver |
julius |
4868d 15h |
/openrisc/trunk/orpsocv2/ |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4872d 20h |
/openrisc/trunk/orpsocv2/ |
480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
4890d 00h |
/openrisc/trunk/orpsocv2/ |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4891d 00h |
/openrisc/trunk/orpsocv2/ |
478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4892d 15h |
/openrisc/trunk/orpsocv2/ |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4893d 00h |
/openrisc/trunk/orpsocv2/ |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4893d 17h |
/openrisc/trunk/orpsocv2/ |
475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4893d 19h |
/openrisc/trunk/orpsocv2/ |
470 |
ORPSoC OR1200 crt0 updates. |
julius |
4897d 19h |
/openrisc/trunk/orpsocv2/ |
468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4898d 21h |
/openrisc/trunk/orpsocv2/ |
466 |
ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README |
julius |
4900d 00h |
/openrisc/trunk/orpsocv2/ |
465 |
ORPSoC SPI flash load Makefile and README updates. |
julius |
4900d 14h |
/openrisc/trunk/orpsocv2/ |
462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4900d 23h |
/openrisc/trunk/orpsocv2/ |
456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4912d 15h |
/openrisc/trunk/orpsocv2/ |
449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
4925d 10h |
/openrisc/trunk/orpsocv2/ |
439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4932d 14h |
/openrisc/trunk/orpsocv2/ |