Rev |
Log message |
Author |
Age |
Path |
537 |
ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. |
julius |
4787d 12h |
/openrisc/trunk/orpsocv2/ |
536 |
ORPSoC - removing duplicate ethmac toplevel file. |
julius |
4791d 02h |
/openrisc/trunk/orpsocv2/ |
535 |
ORPSoC - adding sw tests for l.rfe |
julius |
4792d 16h |
/openrisc/trunk/orpsocv2/ |
530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4800d 01h |
/openrisc/trunk/orpsocv2/ |
528 |
ORPSoC SPI flash programming link script bug fix |
julius |
4805d 00h |
/openrisc/trunk/orpsocv2/ |
506 |
ORPSoC or1200 interrupt and syscall generation test |
julius |
4825d 19h |
/openrisc/trunk/orpsocv2/ |
505 |
OR1200 overflow detection fixup
SPIflash program update
or1200 driver library timer improvement |
julius |
4825d 19h |
/openrisc/trunk/orpsocv2/ |
504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4842d 15h |
/openrisc/trunk/orpsocv2/ |
503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4843d 11h |
/openrisc/trunk/orpsocv2/ |
502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4845d 15h |
/openrisc/trunk/orpsocv2/ |
501 |
ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default |
julius |
4846d 16h |
/openrisc/trunk/orpsocv2/ |
500 |
ORPSoC's System C UART model can now accept input from stdin during simulation to drive consoles etc
ML501 simulation makefile update to allow custom ELFs to be specified |
julius |
4846d 19h |
/openrisc/trunk/orpsocv2/ |
499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4847d 12h |
/openrisc/trunk/orpsocv2/ |
496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
4849d 22h |
/openrisc/trunk/orpsocv2/ |
495 |
ORPSoC adding more accessor functions to Micron SDRAM model. |
julius |
4849d 22h |
/openrisc/trunk/orpsocv2/ |
493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
4863d 00h |
/openrisc/trunk/orpsocv2/ |
492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
4863d 22h |
/openrisc/trunk/orpsocv2/ |
491 |
ORPSoC or1200_monitor update. |
julius |
4864d 09h |
/openrisc/trunk/orpsocv2/ |
489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
4873d 22h |
/openrisc/trunk/orpsocv2/ |
488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
4873d 22h |
/openrisc/trunk/orpsocv2/ |
487 |
ORPSoC main software makefile update |
julius |
4876d 20h |
/openrisc/trunk/orpsocv2/ |
486 |
ORPSoC updates, mainly software, i2c driver |
julius |
4876d 20h |
/openrisc/trunk/orpsocv2/ |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4881d 01h |
/openrisc/trunk/orpsocv2/ |
480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
4898d 05h |
/openrisc/trunk/orpsocv2/ |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4899d 04h |
/openrisc/trunk/orpsocv2/ |
478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4900d 20h |
/openrisc/trunk/orpsocv2/ |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4901d 04h |
/openrisc/trunk/orpsocv2/ |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4901d 22h |
/openrisc/trunk/orpsocv2/ |
475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4902d 00h |
/openrisc/trunk/orpsocv2/ |
470 |
ORPSoC OR1200 crt0 updates. |
julius |
4906d 00h |
/openrisc/trunk/orpsocv2/ |