| Rev |
Log message |
Author |
Age |
Path |
| 417 |
ORPSoC re-adding doc automake files, this time not symlinks |
julius |
5024d 02h |
/openrisc/trunk/orpsocv2/ |
| 416 |
ORPSoC doc cleanup - removing symlinks from automake'd docs build path |
julius |
5024d 02h |
/openrisc/trunk/orpsocv2/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
5024d 03h |
/openrisc/trunk/orpsocv2/ |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
5027d 16h |
/openrisc/trunk/orpsocv2/ |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
5028d 04h |
/openrisc/trunk/orpsocv2/ |
| 410 |
ORPSoC: Adding README in root explaining how to build documentation, and
documentation fixup so it builds properly again. |
julius |
5029d 04h |
/openrisc/trunk/orpsocv2/ |
| 409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
5029d 04h |
/openrisc/trunk/orpsocv2/ |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
5029d 16h |
/openrisc/trunk/orpsocv2/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
5030d 22h |
/openrisc/trunk/orpsocv2/ |
| 398 |
ORPSoCv2 removing generic backend path - not needed |
julius |
5032d 05h |
/openrisc/trunk/orpsocv2/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
5033d 04h |
/openrisc/trunk/orpsocv2/ |
| 396 |
ORPSoCv2 final software fixes...for now. See updated README |
julius |
5036d 02h |
/openrisc/trunk/orpsocv2/ |
| 395 |
ORPSoCv2 moving ethernet tests to correct place |
julius |
5036d 03h |
/openrisc/trunk/orpsocv2/ |
| 394 |
ORPSoCv2 removing unused directories |
julius |
5036d 03h |
/openrisc/trunk/orpsocv2/ |
| 393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
5036d 03h |
/openrisc/trunk/orpsocv2/ |
| 392 |
ORPSoCv2 software path reorganisation stage 1. |
julius |
5036d 19h |
/openrisc/trunk/orpsocv2/ |
| 391 |
Removing modules no longer needed in ORPSoCv2 |
julius |
5037d 20h |
/openrisc/trunk/orpsocv2/ |
| 374 |
ORPSoCv2 adding some files forgotten from last checkin |
julius |
5069d 02h |
/openrisc/trunk/orpsocv2/ |
| 373 |
ORPSoCv2 software update for compatibility with OR toolchain 1.0 |
julius |
5069d 02h |
/openrisc/trunk/orpsocv2/ |
| 364 |
OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.
OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)
OR1200 spec updated to version 0.9, various updates.
OR1200 in ORPSoC and main OR1200 in sync, only difference is defines. |
julius |
5081d 00h |
/openrisc/trunk/orpsocv2/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5081d 09h |
/openrisc/trunk/orpsocv2/ |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5082d 19h |
/openrisc/trunk/orpsocv2/ |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5082d 23h |
/openrisc/trunk/orpsocv2/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5083d 00h |
/openrisc/trunk/orpsocv2/ |
| 358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5083d 08h |
/openrisc/trunk/orpsocv2/ |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5083d 18h |
/openrisc/trunk/orpsocv2/ |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5084d 23h |
/openrisc/trunk/orpsocv2/ |
| 353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5085d 02h |
/openrisc/trunk/orpsocv2/ |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5086d 00h |
/openrisc/trunk/orpsocv2/ |
| 350 |
Adding new OR1200 processor to ORPSoCv2 |
julius |
5086d 04h |
/openrisc/trunk/orpsocv2/ |
