| Rev |
Log message |
Author |
Age |
Path |
| 364 |
OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.
OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)
OR1200 spec updated to version 0.9, various updates.
OR1200 in ORPSoC and main OR1200 in sync, only difference is defines. |
julius |
5026d 02h |
/openrisc/trunk/orpsocv2/rtl/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5026d 11h |
/openrisc/trunk/orpsocv2/rtl/ |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5027d 21h |
/openrisc/trunk/orpsocv2/rtl/ |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5028d 01h |
/openrisc/trunk/orpsocv2/rtl/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5028d 02h |
/openrisc/trunk/orpsocv2/rtl/ |
| 358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5028d 10h |
/openrisc/trunk/orpsocv2/rtl/ |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5028d 20h |
/openrisc/trunk/orpsocv2/rtl/ |
| 353 |
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.
ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""
or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)
ORPmon play around, various changes to low level files. |
julius |
5030d 04h |
/openrisc/trunk/orpsocv2/rtl/ |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5031d 02h |
/openrisc/trunk/orpsocv2/rtl/ |
| 350 |
Adding new OR1200 processor to ORPSoCv2 |
julius |
5031d 06h |
/openrisc/trunk/orpsocv2/rtl/ |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5031d 06h |
/openrisc/trunk/orpsocv2/rtl/ |
| 185 |
Adding single precision FPU to or1200, initial checkin, not fully tested yet |
julius |
5089d 04h |
/openrisc/trunk/orpsocv2/rtl/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5231d 16h |
/openrisc/trunk/orpsocv2/rtl/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5234d 10h |
/openrisc/trunk/orpsocv2/rtl/ |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5258d 15h |
/openrisc/trunk/orpsocv2/rtl/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5271d 07h |
/openrisc/trunk/orpsocv2/rtl/ |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5313d 03h |
/openrisc/trunk/orpsocv2/rtl/ |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5318d 07h |
/openrisc/trunk/orpsocv2/rtl/ |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5328d 23h |
/openrisc/trunk/orpsocv2/rtl/ |
| 54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5339d 06h |
/openrisc/trunk/orpsocv2/rtl/ |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5372d 05h |
/openrisc/trunk/orpsocv2/rtl/ |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5390d 23h |
/openrisc/trunk/orpsocv2/rtl/ |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5406d 10h |
/openrisc/trunk/orpsocv2/rtl/ |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5442d 10h |
/openrisc/trunk/orpsocv2/rtl/ |
| 43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5466d 07h |
/openrisc/trunk/orpsocv2/rtl/ |
| 41 |
Update to or1k top |
julius |
5485d 05h |
/openrisc/trunk/orpsocv2/rtl/ |
| 6 |
Checking in ORPSoCv2 |
julius |
5504d 22h |
/openrisc/trunk/orpsocv2/rtl/ |
