| Rev |
Log message |
Author |
Age |
Path |
| 506 |
ORPSoC or1200 interrupt and syscall generation test |
julius |
4813d 00h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 505 |
OR1200 overflow detection fixup
SPIflash program update
or1200 driver library timer improvement |
julius |
4813d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4829d 21h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4830d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4832d 21h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 501 |
ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default |
julius |
4833d 21h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4834d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4868d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4886d 10h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4888d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4888d 10h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4889d 03h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4896d 09h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4908d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4928d 00h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4934d 15h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
4947d 15h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4956d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
4959d 14h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
4960d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
4961d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4961d 15h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4962d 20h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4965d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 392 |
ORPSoCv2 software path reorganisation stage 1. |
julius |
4968d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 391 |
Removing modules no longer needed in ORPSoCv2 |
julius |
4969d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 373 |
ORPSoCv2 software update for compatibility with OR toolchain 1.0 |
julius |
5001d 00h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 364 |
OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.
OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)
OR1200 spec updated to version 0.9, various updates.
OR1200 in ORPSoC and main OR1200 in sync, only difference is defines. |
julius |
5012d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5013d 08h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 362 |
ORPSoCv2 verilator building working again. Board build fixes to follow |
julius |
5014d 17h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
