| Rev |
Log message |
Author |
Age |
Path |
| 815 |
OR1200 debug unit: prevent deadlock when trap instruction stalls
As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.
The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result. |
yannv |
4285d 07h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 814 |
orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4300d 00h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 807 |
ORPSoC: Commit for bug 85 - add DSX support to OR1200.
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85
Also added software tests, and added these tests to default regression test list |
julius |
4415d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 805 |
ORPSoC: Fix for bug 90 - EPCR on range exception bug
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 |
julius |
4415d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 803 |
ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 |
julius |
4415d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 801 |
ORPSoC: Fix bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4420d 23h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 794 |
ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file
Fixes lint warnings. |
julius |
4454d 09h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 788 |
or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.
Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
julius |
4478d 23h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 679 |
Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used
Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com> |
olof |
4502d 23h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 672 |
ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled
OR1200 RTL fix and software test added. |
julius |
4581d 19h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 655 |
ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation |
julius |
4632d 21h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 619 |
ORPSoC OR1200 fix and regression test for bug 51.
signed-off Julius Baxter
reviewed by Stefan Kristiansson |
julius |
4713d 20h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 618 |
Remove unused parameter Tp |
olof |
4714d 03h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 570 |
Fix white space in ethmac headers |
olof |
4728d 23h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 547 |
ORPSoC dbg_if fix for slow Wishbone slaves |
julius |
4776d 06h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 546 |
ORPSoC update: Fix WB B3 bursting termination on error in WB B3 RAM model |
julius |
4776d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 545 |
ORPSoC - revert unecessary i2c fix - driver oneliner was all that was needed. |
julius |
4783d 01h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 543 |
i2c_master_slave bug fix for slave, potentially holding SDA low when master wants to send stop. |
julius |
4783d 08h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 537 |
ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. |
julius |
4799d 19h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 536 |
ORPSoC - removing duplicate ethmac toplevel file. |
julius |
4803d 09h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4812d 08h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 506 |
ORPSoC or1200 interrupt and syscall generation test |
julius |
4838d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 505 |
OR1200 overflow detection fixup
SPIflash program update
or1200 driver library timer improvement |
julius |
4838d 02h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4854d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 503 |
ORPSoC's or1200 defines fix to indicate we don't actually have I/DMMU invalidate registers. |
julius |
4855d 18h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4857d 22h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 501 |
ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default |
julius |
4858d 23h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4859d 19h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4893d 08h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
| 479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4911d 11h |
/openrisc/trunk/orpsocv2/rtl/verilog/ |
