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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] - Rev 412

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Rev Log message Author Age Path
412 ORPSoC update - Rearranged Xilinx ML501, simulations working again. julius 4992d 05h /openrisc/trunk/orpsocv2/rtl/verilog/
411 Improved ethmac testbench and software.

Renamed some OR1200 library functions to be more generic.

Fixed bug with versatile_mem_ctrl for Actel board.

Added ability to simulate gatelevel modules alongside RTL modules
in board build.		 julius 4992d 17h /openrisc/trunk/orpsocv2/rtl/verilog/
409 ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation.		 julius 4993d 17h /openrisc/trunk/orpsocv2/rtl/verilog/
408 ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. julius 4994d 05h /openrisc/trunk/orpsocv2/rtl/verilog/
403 ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. julius 4995d 10h /openrisc/trunk/orpsocv2/rtl/verilog/
397 ORPSoCv2:

doc/ path added, with Texinfo documentation. Still a work in progress.

VPI files updated.

OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.

Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build.		 julius 4997d 16h /openrisc/trunk/orpsocv2/rtl/verilog/
392 ORPSoCv2 software path reorganisation stage 1. julius 5001d 07h /openrisc/trunk/orpsocv2/rtl/verilog/
391 Removing modules no longer needed in ORPSoCv2 julius 5002d 08h /openrisc/trunk/orpsocv2/rtl/verilog/
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5033d 15h /openrisc/trunk/orpsocv2/rtl/verilog/
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5045d 12h /openrisc/trunk/orpsocv2/rtl/verilog/
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5045d 22h /openrisc/trunk/orpsocv2/rtl/verilog/
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 5047d 07h /openrisc/trunk/orpsocv2/rtl/verilog/
361 OPRSoCv2 - adding things left out in last check-in julius 5047d 12h /openrisc/trunk/orpsocv2/rtl/verilog/
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5047d 12h /openrisc/trunk/orpsocv2/rtl/verilog/
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5047d 21h /openrisc/trunk/orpsocv2/rtl/verilog/
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 5048d 06h /openrisc/trunk/orpsocv2/rtl/verilog/
353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.		 julius 5049d 14h /openrisc/trunk/orpsocv2/rtl/verilog/
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5050d 12h /openrisc/trunk/orpsocv2/rtl/verilog/
350 Adding new OR1200 processor to ORPSoCv2 julius 5050d 16h /openrisc/trunk/orpsocv2/rtl/verilog/
348 First stage of ORPSoCv2 update - more to come julius 5050d 16h /openrisc/trunk/orpsocv2/rtl/verilog/
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5108d 14h /openrisc/trunk/orpsocv2/rtl/verilog/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5251d 03h /openrisc/trunk/orpsocv2/rtl/verilog/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5253d 21h /openrisc/trunk/orpsocv2/rtl/verilog/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5278d 01h /openrisc/trunk/orpsocv2/rtl/verilog/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5290d 17h /openrisc/trunk/orpsocv2/rtl/verilog/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5332d 13h /openrisc/trunk/orpsocv2/rtl/verilog/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5337d 17h /openrisc/trunk/orpsocv2/rtl/verilog/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5348d 10h /openrisc/trunk/orpsocv2/rtl/verilog/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5358d 17h /openrisc/trunk/orpsocv2/rtl/verilog/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5391d 16h /openrisc/trunk/orpsocv2/rtl/verilog/

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