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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] - Rev 853

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853 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>		 olof 4232d 14h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
850 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4247d 06h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
849 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4247d 06h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
848 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4247d 06h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
815 OR1200 debug unit: prevent deadlock when trap instruction stalls

As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.

The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result.		 yannv 4268d 00h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
814 orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4282d 16h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
807 ORPSoC: Commit for bug 85 - add DSX support to OR1200.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85

Also added software tests, and added these tests to default regression test list		 julius 4398d 10h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
805 ORPSoC: Fix for bug 90 - EPCR on range exception bug

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90		 julius 4398d 10h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
803 ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91		 julius 4398d 10h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
801 ORPSoC: Fix bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88		 julius 4403d 16h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
794 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file

Fixes lint warnings.		 julius 4437d 01h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 julius 4461d 15h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
679 Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4485d 15h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
672 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled

OR1200 RTL fix and software test added.		 julius 4564d 11h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson		 julius 4696d 12h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
537 ORPSoC or1200 fix for l.rfe bug, and when multiply is disabled. julius 4782d 11h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
505 OR1200 overflow detection fixup

SPIflash program update

or1200 driver library timer improvement		 julius 4820d 19h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4837d 15h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default		 julius 4840d 15h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
501 ORPSoC or1200 mult/mac/divide unit serial arith bug fixed.
ORPSoC or1200 defines now use serial divide by default		 julius 4841d 15h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4842d 11h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4876d 00h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4894d 04h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
478 ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. julius 4895d 19h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
477 ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.		 julius 4896d 04h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
476 ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. julius 4896d 21h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 4904d 03h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4915d 19h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4942d 09h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4955d 09h /openrisc/trunk/orpsocv2/rtl/verilog/or1200/

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