Rev |
Log message |
Author |
Age |
Path |
78 |
Fixed typo in Silos workaround script |
rherveille |
5187d 20h |
/openrisc/trunk/orpsocv2/sim/ |
77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5187d 20h |
/openrisc/trunk/orpsocv2/sim/ |
76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5188d 20h |
/openrisc/trunk/orpsocv2/sim/ |
70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5235d 10h |
/openrisc/trunk/orpsocv2/sim/ |
69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5235d 11h |
/openrisc/trunk/orpsocv2/sim/ |
68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5238d 03h |
/openrisc/trunk/orpsocv2/sim/ |
67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5238d 06h |
/openrisc/trunk/orpsocv2/sim/ |
66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5258d 04h |
/openrisc/trunk/orpsocv2/sim/ |
64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5265d 05h |
/openrisc/trunk/orpsocv2/sim/ |
63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5275d 02h |
/openrisc/trunk/orpsocv2/sim/ |
58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5316d 22h |
/openrisc/trunk/orpsocv2/sim/ |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5322d 02h |
/openrisc/trunk/orpsocv2/sim/ |
55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5332d 18h |
/openrisc/trunk/orpsocv2/sim/ |
54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5343d 01h |
/openrisc/trunk/orpsocv2/sim/ |
53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5361d 02h |
/openrisc/trunk/orpsocv2/sim/ |
51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5376d 00h |
/openrisc/trunk/orpsocv2/sim/ |
49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5394d 18h |
/openrisc/trunk/orpsocv2/sim/ |
44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5446d 05h |
/openrisc/trunk/orpsocv2/sim/ |
43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5470d 02h |
/openrisc/trunk/orpsocv2/sim/ |
42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5485d 23h |
/openrisc/trunk/orpsocv2/sim/ |
40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5490d 05h |
/openrisc/trunk/orpsocv2/sim/ |
36 |
Better clean rule in makefile |
julius |
5504d 06h |
/openrisc/trunk/orpsocv2/sim/ |
6 |
Checking in ORPSoCv2 |
julius |
5508d 17h |
/openrisc/trunk/orpsocv2/sim/ |