| Rev |
Log message |
Author |
Age |
Path |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4927d 22h |
/openrisc/trunk/orpsocv2/sw/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4934d 14h |
/openrisc/trunk/orpsocv2/sw/ |
| 431 |
Updated and move OR1200 supplementary manual.
or_debug_proxy GDB RSP interface fix.
ORPSoC S/W and makefile updates. |
julius |
4940d 21h |
/openrisc/trunk/orpsocv2/sw/ |
| 426 |
ORPSoC update
Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.
ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued... |
julius |
4947d 13h |
/openrisc/trunk/orpsocv2/sw/ |
| 425 |
ORPSoC update:
GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.
Documentation updated.
Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.
Updated Or1200 tests to report test success value and then
exit with value 0. |
julius |
4947d 14h |
/openrisc/trunk/orpsocv2/sw/ |
| 415 |
ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash. |
julius |
4955d 23h |
/openrisc/trunk/orpsocv2/sw/ |
| 412 |
ORPSoC update - Rearranged Xilinx ML501, simulations working again. |
julius |
4959d 13h |
/openrisc/trunk/orpsocv2/sw/ |
| 411 |
Improved ethmac testbench and software.
Renamed some OR1200 library functions to be more generic.
Fixed bug with versatile_mem_ctrl for Actel board.
Added ability to simulate gatelevel modules alongside RTL modules
in board build. |
julius |
4960d 01h |
/openrisc/trunk/orpsocv2/sw/ |
| 409 |
ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
Updated documentation. |
julius |
4961d 00h |
/openrisc/trunk/orpsocv2/sw/ |
| 408 |
ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too. |
julius |
4961d 13h |
/openrisc/trunk/orpsocv2/sw/ |
| 403 |
ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly. |
julius |
4962d 18h |
/openrisc/trunk/orpsocv2/sw/ |
| 397 |
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work in progress.
VPI files updated.
OR1200 l.maci instruction test added. highlighting bug with immediate field for that instruction.
Various cycle accurate model updates. Now uses orpsoc-defines.v (processed C-compat. version) to build. |
julius |
4965d 00h |
/openrisc/trunk/orpsocv2/sw/ |
| 396 |
ORPSoCv2 final software fixes...for now. See updated README |
julius |
4967d 23h |
/openrisc/trunk/orpsocv2/sw/ |
| 395 |
ORPSoCv2 moving ethernet tests to correct place |
julius |
4967d 23h |
/openrisc/trunk/orpsocv2/sw/ |
| 394 |
ORPSoCv2 removing unused directories |
julius |
4967d 23h |
/openrisc/trunk/orpsocv2/sw/ |
| 393 |
ORPSoCv2 software rearrangement in progress. Basic tests should now run again. |
julius |
4967d 23h |
/openrisc/trunk/orpsocv2/sw/ |
| 392 |
ORPSoCv2 software path reorganisation stage 1. |
julius |
4968d 15h |
/openrisc/trunk/orpsocv2/sw/ |
| 374 |
ORPSoCv2 adding some files forgotten from last checkin |
julius |
5000d 22h |
/openrisc/trunk/orpsocv2/sw/ |
| 373 |
ORPSoCv2 software update for compatibility with OR toolchain 1.0 |
julius |
5000d 22h |
/openrisc/trunk/orpsocv2/sw/ |
| 363 |
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug interface disabled for now in both RTL and System C top level.
Profiled building of cycle-accurate model now done correctly. |
julius |
5013d 06h |
/openrisc/trunk/orpsocv2/sw/ |
| 361 |
OPRSoCv2 - adding things left out in last check-in |
julius |
5014d 20h |
/openrisc/trunk/orpsocv2/sw/ |
| 360 |
First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken |
julius |
5014d 20h |
/openrisc/trunk/orpsocv2/sw/ |
| 358 |
OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.
Updated OR1200 in ORPSoCv2 and OR1200 project. |
julius |
5015d 05h |
/openrisc/trunk/orpsocv2/sw/ |
| 356 |
Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added
Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""
* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests |
julius |
5015d 14h |
/openrisc/trunk/orpsocv2/sw/ |
| 354 |
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz. |
julius |
5016d 20h |
/openrisc/trunk/orpsocv2/sw/ |
| 351 |
OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO |
julius |
5017d 20h |
/openrisc/trunk/orpsocv2/sw/ |
| 349 |
ORPSoCv2 update with new software and makefile update |
julius |
5018d 00h |
/openrisc/trunk/orpsocv2/sw/ |
| 348 |
First stage of ORPSoCv2 update - more to come |
julius |
5018d 00h |
/openrisc/trunk/orpsocv2/sw/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5221d 05h |
/openrisc/trunk/orpsocv2/sw/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5241d 03h |
/openrisc/trunk/orpsocv2/sw/ |
