OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [branch_qmem/] [or1200/] - Rev 916

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8023d 11h /or1k/branches/branch_qmem/or1200/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8039d 15h /or1k/branches/branch_qmem/or1200/
871 Generic flip-flop based memory macro for register file. lampret 8075d 21h /or1k/branches/branch_qmem/or1200/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8075d 21h /or1k/branches/branch_qmem/or1200/
869 Added generic flip-flop based memory macro instantiation. lampret 8075d 21h /or1k/branches/branch_qmem/or1200/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8146d 21h /or1k/branches/branch_qmem/or1200/
794 Added again just recently removed full_case directive lampret 8146d 21h /or1k/branches/branch_qmem/or1200/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8146d 21h /or1k/branches/branch_qmem/or1200/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8146d 21h /or1k/branches/branch_qmem/or1200/
788 Some of the warnings fixed. lampret 8146d 22h /or1k/branches/branch_qmem/or1200/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8147d 18h /or1k/branches/branch_qmem/or1200/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8147d 18h /or1k/branches/branch_qmem/or1200/
776 Updated defines. lampret 8147d 18h /or1k/branches/branch_qmem/or1200/
775 Optimized cache controller FSM. lampret 8147d 18h /or1k/branches/branch_qmem/or1200/
774 Removed old files. lampret 8147d 19h /or1k/branches/branch_qmem/or1200/
737 Added alternative for critical path in DU. lampret 8162d 13h /or1k/branches/branch_qmem/or1200/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8165d 12h /or1k/branches/branch_qmem/or1200/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8165d 12h /or1k/branches/branch_qmem/or1200/
668 Lapsus fixed. simons 8189d 22h /or1k/branches/branch_qmem/or1200/
663 No longer using async rst as sync reset for the counter. lampret 8192d 12h /or1k/branches/branch_qmem/or1200/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8193d 09h /or1k/branches/branch_qmem/or1200/
636 Fixed combinational loops. lampret 8202d 17h /or1k/branches/branch_qmem/or1200/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8207d 12h /or1k/branches/branch_qmem/or1200/
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8212d 05h /or1k/branches/branch_qmem/or1200/
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8215d 23h /or1k/branches/branch_qmem/or1200/
596 SR[TEE] should be zero after reset. lampret 8216d 04h /or1k/branches/branch_qmem/or1200/
595 Fixed 'the NPC single-step fix'. lampret 8216d 23h /or1k/branches/branch_qmem/or1200/
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8217d 05h /or1k/branches/branch_qmem/or1200/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8220d 07h /or1k/branches/branch_qmem/or1200/
571 Changed alignment exception EPCR. Not tested yet. lampret 8220d 16h /or1k/branches/branch_qmem/or1200/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.