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[/] [or1k/] [branches/] [stable_0_1_x/] - Rev 1006

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Rev Log message Author Age Path
1006 Import ivang 7982d 08h /or1k/branches/stable_0_1_x/
1005 Import ivang 7982d 08h /or1k/branches/stable_0_1_x/
1004 Now every ramdisk image should have init program. simons 7982d 17h /or1k/branches/stable_0_1_x/
1003 cuc temporary files are deleted upon exiting markom 7982d 17h /or1k/branches/stable_0_1_x/
1002 Now every ramdisk image should have init program. simons 7982d 17h /or1k/branches/stable_0_1_x/
1001 fixed load/store state machine verilog generation errors markom 7982d 17h /or1k/branches/stable_0_1_x/
1000 IC/DC cache enable routines fixed. simons 7982d 18h /or1k/branches/stable_0_1_x/
999 Now every ramdisk image should have init program. simons 7982d 18h /or1k/branches/stable_0_1_x/
998 added missing fout initialization markom 7982d 20h /or1k/branches/stable_0_1_x/
997 PRINTF should be used instead of printf; command redirection repaired markom 7982d 21h /or1k/branches/stable_0_1_x/
996 some minor bugs fixed markom 7983d 20h /or1k/branches/stable_0_1_x/
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 7984d 03h /or1k/branches/stable_0_1_x/
993 Fixed IMMU bug. lampret 7984d 03h /or1k/branches/stable_0_1_x/
992 A bug when cache enabled and bus error comes fixed. simons 7984d 12h /or1k/branches/stable_0_1_x/
991 Different memory controller. simons 7984d 13h /or1k/branches/stable_0_1_x/
990 Test is now complete. simons 7984d 13h /or1k/branches/stable_0_1_x/
989 c++ is making problems so, for now, it is excluded. simons 7985d 21h /or1k/branches/stable_0_1_x/
988 ORP architecture supported. simons 7986d 12h /or1k/branches/stable_0_1_x/
987 ORP architecture supported. simons 7986d 19h /or1k/branches/stable_0_1_x/
986 outputs out of function are not registered anymore markom 7986d 20h /or1k/branches/stable_0_1_x/
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7987d 08h /or1k/branches/stable_0_1_x/
984 Disable SB until it is tested lampret 7987d 08h /or1k/branches/stable_0_1_x/
983 First checkin lampret 7987d 10h /or1k/branches/stable_0_1_x/
982 Moved to sim/bin lampret 7987d 10h /or1k/branches/stable_0_1_x/
981 First checkin. lampret 7987d 10h /or1k/branches/stable_0_1_x/
980 Removed sim.tcl that shouldn't be here. lampret 7987d 10h /or1k/branches/stable_0_1_x/
979 Removed old test case binaries. lampret 7987d 10h /or1k/branches/stable_0_1_x/
978 Added variable delay for SRAM. lampret 7987d 10h /or1k/branches/stable_0_1_x/
977 Added store buffer. lampret 7987d 10h /or1k/branches/stable_0_1_x/
976 Added store buffer lampret 7987d 10h /or1k/branches/stable_0_1_x/

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