OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] - Rev 1766

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5602d 05h /or1k/branches/stable_0_2_x/or1ksim/
1646 This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'. 6749d 08h /or1k/branches/stable_0_2_x/or1ksim/
1645 Or1ksim release 0.2.0 nogj 6749d 08h /or1k/branches/stable_0_2_x/or1ksim/
1644 Update ChangeLog nogj 6749d 08h /or1k/branches/stable_0_2_x/or1ksim/
1643 Fix segmentation fault if setting a breakpoint on a non-existing label nogj 6749d 08h /or1k/branches/stable_0_2_x/or1ksim/
1642 Release 0.2.0-rc3 nogj 6760d 10h /or1k/branches/stable_0_2_x/or1ksim/
1641 Update ChangeLog nogj 6760d 10h /or1k/branches/stable_0_2_x/or1ksim/
1640 Upgrade cvs2cl.pl to version 2.59 nogj 6760d 10h /or1k/branches/stable_0_2_x/or1ksim/
1637 *** empty log message *** rezso 6763d 18h /or1k/branches/stable_0_2_x/or1ksim/
1619 Fixed types in function declaration jcastillo 6783d 20h /or1k/branches/stable_0_2_x/or1ksim/
1614 CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU) phoenix 6794d 03h /or1k/branches/stable_0_2_x/or1ksim/
1610 Update ChangeLog nogj 6802d 14h /or1k/branches/stable_0_2_x/or1ksim/
1609 0.2.0-rc2 release nogj 6802d 15h /or1k/branches/stable_0_2_x/or1ksim/
1608 Avoid scheduleing too many jobs, potentially underflowing the scheduler stack nogj 6803d 09h /or1k/branches/stable_0_2_x/or1ksim/
1607 Don't drop cycles from the scheduler nogj 6803d 09h /or1k/branches/stable_0_2_x/or1ksim/
1606 fix uninitialized reads phoenix 6803d 14h /or1k/branches/stable_0_2_x/or1ksim/
1605 Execute l.ff1 instruction nogj 6810d 09h /or1k/branches/stable_0_2_x/or1ksim/
1604 Fix dumphex/dumpverilog to not do unaligned memory access nogj 6810d 09h /or1k/branches/stable_0_2_x/or1ksim/
1598 Handle ethernet addresses as an address and not as an int nogj 6822d 11h /or1k/branches/stable_0_2_x/or1ksim/
1597 Fix parsing the destination register nogj 6822d 11h /or1k/branches/stable_0_2_x/or1ksim/
1596 Fix handling of eof in the sim cli nogj 6822d 11h /or1k/branches/stable_0_2_x/or1ksim/
1595 Add default immu/dmmu page size nogj 6822d 11h /or1k/branches/stable_0_2_x/or1ksim/
1594 Fix the case of is_power2(0) nogj 6822d 11h /or1k/branches/stable_0_2_x/or1ksim/
1593 Don't kill sim on second ctrl+c if the cli prompt has already been shown nogj 6822d 11h /or1k/branches/stable_0_2_x/or1ksim/
1590 Added l.fl1 lampret 6825d 08h /or1k/branches/stable_0_2_x/or1ksim/
1589 Make -d channel be equivalent to -d +channel nogj 6828d 20h /or1k/branches/stable_0_2_x/or1ksim/
1588 Correct INT_MAX->INT32_MAX nogj 6828d 20h /or1k/branches/stable_0_2_x/or1ksim/
1586 Charles Qi
Fix memory handling on big endian machines		 nogj 6833d 13h /or1k/branches/stable_0_2_x/or1ksim/
1585 added missing exception, fixes segfault with trap exception phoenix 6839d 05h /or1k/branches/stable_0_2_x/or1ksim/
1584 usability improvments phoenix 6840d 04h /or1k/branches/stable_0_2_x/or1ksim/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.