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[/] [or1k/] [tags/] [nog_patch_35/] - Rev 414

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Rev Log message Author Age Path
414 Stack section should not be loaded into mamory. simons 8282d 12h /or1k/tags/nog_patch_35/
413 some section changes markom 8282d 14h /or1k/tags/nog_patch_35/
412 *** empty log message *** simons 8282d 14h /or1k/tags/nog_patch_35/
411 acv uart testsuite now works (without modem test) markom 8282d 17h /or1k/tags/nog_patch_35/
410 MMU test added. simons 8283d 11h /or1k/tags/nog_patch_35/
409 some minor changes to or1ksim; Testbench except.s modified. Interrupt test almost finished for uart ACV. markom 8283d 17h /or1k/tags/nog_patch_35/
408 Fixed errant rx_bd_num erez 8284d 14h /or1k/tags/nog_patch_35/
406 Renamed ethernet's RX_BD_ADR to RX_BD_NUM erez 8284d 16h /or1k/tags/nog_patch_35/
405 Stepping trough l.jal and l.jalr fixed. simons 8285d 18h /or1k/tags/nog_patch_35/
404 is_delayed() is used outside this file. simons 8285d 18h /or1k/tags/nog_patch_35/
403 Prompt changed because ddd requires (gdb). simons 8285d 18h /or1k/tags/nog_patch_35/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8285d 22h /or1k/tags/nog_patch_35/
401 *** empty log message *** simons 8289d 08h /or1k/tags/nog_patch_35/
400 force_dslot_fetch does not work - allways zero. simons 8289d 08h /or1k/tags/nog_patch_35/
399 Trap insn couses break after exits ex_insn. simons 8289d 08h /or1k/tags/nog_patch_35/
398 added register field defines ivang 8291d 13h /or1k/tags/nog_patch_35/
397 removed or16 architecture markom 8291d 15h /or1k/tags/nog_patch_35/
396 added missing file markom 8291d 17h /or1k/tags/nog_patch_35/
395 removed obsolete dependency and history from cpu section markom 8291d 19h /or1k/tags/nog_patch_35/
394 dependency joined with dependstats; history moved to sim section markom 8291d 20h /or1k/tags/nog_patch_35/
393 messages: exception on many places changed to abort markom 8291d 20h /or1k/tags/nog_patch_35/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8292d 04h /or1k/tags/nog_patch_35/
390 Changed instantiation name of VS RAMs. lampret 8292d 06h /or1k/tags/nog_patch_35/
389 Changed default delay for load and store in superscalar cpu. lampret 8292d 06h /or1k/tags/nog_patch_35/
388 Added comments for cpu section. lampret 8292d 06h /or1k/tags/nog_patch_35/
387 Now FPGA and ASIC target are separate. lampret 8292d 07h /or1k/tags/nog_patch_35/
386 Fixed VS RAM instantiation - again. lampret 8292d 07h /or1k/tags/nog_patch_35/
385 check testbench now modified to work with new report output markom 8292d 14h /or1k/tags/nog_patch_35/
384 modified simmem.cfg structure! ADD > BEFORE EACH LINE! markom 8292d 15h /or1k/tags/nog_patch_35/
383 modified simmem.cfg structure! ADD markom 8292d 15h /or1k/tags/nog_patch_35/

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