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[/] [or1k/] [tags/] [nog_patch_42/] - Rev 414

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Rev Log message Author Age Path
414 Stack section should not be loaded into mamory. simons 8283d 02h /or1k/tags/nog_patch_42/
413 some section changes markom 8283d 03h /or1k/tags/nog_patch_42/
412 *** empty log message *** simons 8283d 04h /or1k/tags/nog_patch_42/
411 acv uart testsuite now works (without modem test) markom 8283d 07h /or1k/tags/nog_patch_42/
410 MMU test added. simons 8284d 01h /or1k/tags/nog_patch_42/
409 some minor changes to or1ksim; Testbench except.s modified. Interrupt test almost finished for uart ACV. markom 8284d 07h /or1k/tags/nog_patch_42/
408 Fixed errant rx_bd_num erez 8285d 03h /or1k/tags/nog_patch_42/
406 Renamed ethernet's RX_BD_ADR to RX_BD_NUM erez 8285d 06h /or1k/tags/nog_patch_42/
405 Stepping trough l.jal and l.jalr fixed. simons 8286d 07h /or1k/tags/nog_patch_42/
404 is_delayed() is used outside this file. simons 8286d 07h /or1k/tags/nog_patch_42/
403 Prompt changed because ddd requires (gdb). simons 8286d 07h /or1k/tags/nog_patch_42/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8286d 12h /or1k/tags/nog_patch_42/
401 *** empty log message *** simons 8289d 22h /or1k/tags/nog_patch_42/
400 force_dslot_fetch does not work - allways zero. simons 8289d 22h /or1k/tags/nog_patch_42/
399 Trap insn couses break after exits ex_insn. simons 8289d 22h /or1k/tags/nog_patch_42/
398 added register field defines ivang 8292d 03h /or1k/tags/nog_patch_42/
397 removed or16 architecture markom 8292d 05h /or1k/tags/nog_patch_42/
396 added missing file markom 8292d 07h /or1k/tags/nog_patch_42/
395 removed obsolete dependency and history from cpu section markom 8292d 09h /or1k/tags/nog_patch_42/
394 dependency joined with dependstats; history moved to sim section markom 8292d 10h /or1k/tags/nog_patch_42/
393 messages: exception on many places changed to abort markom 8292d 10h /or1k/tags/nog_patch_42/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8292d 18h /or1k/tags/nog_patch_42/
390 Changed instantiation name of VS RAMs. lampret 8292d 20h /or1k/tags/nog_patch_42/
389 Changed default delay for load and store in superscalar cpu. lampret 8292d 20h /or1k/tags/nog_patch_42/
388 Added comments for cpu section. lampret 8292d 20h /or1k/tags/nog_patch_42/
387 Now FPGA and ASIC target are separate. lampret 8292d 21h /or1k/tags/nog_patch_42/
386 Fixed VS RAM instantiation - again. lampret 8292d 21h /or1k/tags/nog_patch_42/
385 check testbench now modified to work with new report output markom 8293d 03h /or1k/tags/nog_patch_42/
384 modified simmem.cfg structure! ADD > BEFORE EACH LINE! markom 8293d 05h /or1k/tags/nog_patch_42/
383 modified simmem.cfg structure! ADD markom 8293d 05h /or1k/tags/nog_patch_42/

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