OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_46/] - Rev 810

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
810 This commit was generated by cvs2svn to compensate for changes in r809,
which included commits to RCS files with non-trunk default branches.		 simons 8125d 18h /or1k/tags/nog_patch_46/
808 Elf support added. simons 8125d 19h /or1k/tags/nog_patch_46/
807 sched files moved to support dir markom 8126d 21h /or1k/tags/nog_patch_46/
806 uart now partially uses scheduler markom 8126d 21h /or1k/tags/nog_patch_46/
805 kbd, fb, vga devices now uses scheduler markom 8126d 22h /or1k/tags/nog_patch_46/
804 memory regions can now overlap with MC -- not according to MC spec markom 8127d 16h /or1k/tags/nog_patch_46/
803 Free irq handler fixed. simons 8130d 09h /or1k/tags/nog_patch_46/
802 Cache and tick timer tests fixed. simons 8131d 20h /or1k/tags/nog_patch_46/
801 l.muli instruction added markom 8133d 16h /or1k/tags/nog_patch_46/
800 Bug fixed. simons 8134d 13h /or1k/tags/nog_patch_46/
799 Wrapping around 512k boundary to simulate real hw. simons 8138d 07h /or1k/tags/nog_patch_46/
798 Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary. simons 8138d 07h /or1k/tags/nog_patch_46/
797 Changed hardcoded address for fake MC to use a define. lampret 8138d 08h /or1k/tags/nog_patch_46/
796 Removed unused ports wb_clki and wb_rst_i lampret 8138d 08h /or1k/tags/nog_patch_46/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8138d 12h /or1k/tags/nog_patch_46/
794 Added again just recently removed full_case directive lampret 8138d 12h /or1k/tags/nog_patch_46/
793 Added synthesis off/on for timescale.v included file. lampret 8138d 12h /or1k/tags/nog_patch_46/
792 Fixed port names that changed. lampret 8138d 12h /or1k/tags/nog_patch_46/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8138d 12h /or1k/tags/nog_patch_46/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8138d 12h /or1k/tags/nog_patch_46/
789 Added response from memory controller (addr 0x60000000) lampret 8138d 13h /or1k/tags/nog_patch_46/
788 Some of the warnings fixed. lampret 8138d 14h /or1k/tags/nog_patch_46/
787 Added romfs.tgz lampret 8139d 08h /or1k/tags/nog_patch_46/
786 Moved UCF constraint file to the backend directory. lampret 8139d 08h /or1k/tags/nog_patch_46/
785 Added XSV specific documentation. lampret 8139d 08h /or1k/tags/nog_patch_46/
784 Added soem missing files. lampret 8139d 08h /or1k/tags/nog_patch_46/
783 Added sim directory and sub files/dirs. lampret 8139d 08h /or1k/tags/nog_patch_46/
782 Added the old SW directory. It needs to be updated for the new ORP environment and test cases moved to sw directory. lampret 8139d 08h /or1k/tags/nog_patch_46/
781 Added design compiler scripts. However these are not ready for use yet .... They need to be updated for the ORP sources and ORP sources need to be updated as well. lampret 8139d 09h /or1k/tags/nog_patch_46/
780 Added libraries. lampret 8139d 09h /or1k/tags/nog_patch_46/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.