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[/] [or1k/] [tags/] [nog_patch_53/] [or1ksim/] [cpu/] - Rev 1765

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1765 root 5578d 12h /or1k/tags/nog_patch_53/or1ksim/cpu/
1431 This commit was manufactured by cvs2svn to create tag 'nog_patch_53'. 7018d 19h /or1k/tags/nog_patch_53/or1ksim/cpu/
1430 Log SPR_SR in the execution log nogj 7018d 19h /or1k/tags/nog_patch_53/or1ksim/cpu/
1428 Remove useless indirection: check_depend()->depend_operands() nogj 7018d 19h /or1k/tags/nog_patch_53/or1ksim/cpu/
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7018d 19h /or1k/tags/nog_patch_53/or1ksim/cpu/
1402 Do what dc_clock() did in mtspr() and remove it nogj 7018d 19h /or1k/tags/nog_patch_53/or1ksim/cpu/
1398 Correct incorrect calls to eval_direct8 nogj 7018d 19h /or1k/tags/nog_patch_53/or1ksim/cpu/
1386 Rework exception handling nogj 7024d 23h /or1k/tags/nog_patch_53/or1ksim/cpu/
1384 Fix the parameters to the l.ff1/l.maci instructions nogj 7033d 23h /or1k/tags/nog_patch_53/or1ksim/cpu/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7033d 23h /or1k/tags/nog_patch_53/or1ksim/cpu/
1376 aclocal && autoconf && automake phoenix 7052d 23h /or1k/tags/nog_patch_53/or1ksim/cpu/
1375 Remove FAST_SIM, it nolonger provides a speed up nogj 7059d 14h /or1k/tags/nog_patch_53/or1ksim/cpu/
1362 initialise dev_mem->chip_select in register_memory nogj 7059d 14h /or1k/tags/nog_patch_53/or1ksim/cpu/
1359 Pass private data in readfunc/writefunc callbacks nogj 7059d 14h /or1k/tags/nog_patch_53/or1ksim/cpu/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7059d 14h /or1k/tags/nog_patch_53/or1ksim/cpu/
1354 typing fixes phoenix 7067d 20h /or1k/tags/nog_patch_53/or1ksim/cpu/
1353 Modularise simulator command parsing nogj 7068d 17h /or1k/tags/nog_patch_53/or1ksim/cpu/
1352 Optimise execution history tracking nogj 7068d 17h /or1k/tags/nog_patch_53/or1ksim/cpu/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7068d 17h /or1k/tags/nog_patch_53/or1ksim/cpu/
1346 Remove the global op structure nogj 7081d 21h /or1k/tags/nog_patch_53/or1ksim/cpu/
1345 Fix out-of-tree builds nogj 7081d 21h /or1k/tags/nog_patch_53/or1ksim/cpu/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7081d 21h /or1k/tags/nog_patch_53/or1ksim/cpu/
1343 * Fix warnings in insnset.c and execute.c nogj 7081d 21h /or1k/tags/nog_patch_53/or1ksim/cpu/
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.		 nogj 7081d 21h /or1k/tags/nog_patch_53/or1ksim/cpu/
1341 Mark wich operand is the destination operand in the architechture definition nogj 7081d 22h /or1k/tags/nog_patch_53/or1ksim/cpu/
1338 l.ff1 instruction added andreje 7097d 19h /or1k/tags/nog_patch_53/or1ksim/cpu/
1324 memory access functions fixes phoenix 7179d 13h /or1k/tags/nog_patch_53/or1ksim/cpu/
1323 Adrian Wise: or1ksim bugfix & Solaris build phoenix 7180d 19h /or1k/tags/nog_patch_53/or1ksim/cpu/
1321 some tests rely on exit(0) as a last std output text to pass phoenix 7183d 12h /or1k/tags/nog_patch_53/or1ksim/cpu/
1319 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7185d 12h /or1k/tags/nog_patch_53/or1ksim/cpu/

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