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[/] [or1k/] [tags/] [nog_patch_58/] [or1ksim/] [cache/] - Rev 1765

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Rev Log message Author Age Path
1765 root 5562d 15h /or1k/tags/nog_patch_58/or1ksim/cache/
1441 This commit was manufactured by cvs2svn to create tag 'nog_patch_58'. 7002d 22h /or1k/tags/nog_patch_58/or1ksim/cache/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7002d 22h /or1k/tags/nog_patch_58/or1ksim/cache/
1406 Fix the declaration of `sec' in reg_ic_sec nogj 7002d 22h /or1k/tags/nog_patch_58/or1ksim/cache/
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7002d 22h /or1k/tags/nog_patch_58/or1ksim/cache/
1402 Do what dc_clock() did in mtspr() and remove it nogj 7002d 22h /or1k/tags/nog_patch_58/or1ksim/cache/
1386 Rework exception handling nogj 7009d 01h /or1k/tags/nog_patch_58/or1ksim/cache/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7018d 02h /or1k/tags/nog_patch_58/or1ksim/cache/
1376 aclocal && autoconf && automake phoenix 7037d 02h /or1k/tags/nog_patch_58/or1ksim/cache/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7043d 17h /or1k/tags/nog_patch_58/or1ksim/cache/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7052d 20h /or1k/tags/nog_patch_58/or1ksim/cache/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7066d 00h /or1k/tags/nog_patch_58/or1ksim/cache/
1308 Gyorgy Jeney: extensive cleanup phoenix 7257d 14h /or1k/tags/nog_patch_58/or1ksim/cache/
1249 Downgrading back to automake-1.4 lampret 7422d 14h /or1k/tags/nog_patch_58/or1ksim/cache/
1117 Ignore generated files for CVS purposes sfurman 7765d 15h /or1k/tags/nog_patch_58/or1ksim/cache/
1099 cvs bug fixed markom 7852d 02h /or1k/tags/nog_patch_58/or1ksim/cache/
1085 Bug fixed. simons 7864d 16h /or1k/tags/nog_patch_58/or1ksim/cache/
997 PRINTF should be used instead of printf; command redirection repaired markom 7954d 05h /or1k/tags/nog_patch_58/or1ksim/cache/
992 A bug when cache enabled and bus error comes fixed. simons 7955d 20h /or1k/tags/nog_patch_58/or1ksim/cache/
970 Testbench is now running on ORP architecture platform. simons 7961d 16h /or1k/tags/nog_patch_58/or1ksim/cache/
884 code cleaning - a lot of global variables moved to runtime struct markom 7998d 03h /or1k/tags/nog_patch_58/or1ksim/cache/
876 Beta release of ATA simulation rherveille 8005d 15h /or1k/tags/nog_patch_58/or1ksim/cache/
638 TLBTR CI bit is now working properly. simons 8156d 17h /or1k/tags/nog_patch_58/or1ksim/cache/
631 Real cache access is simulated now. simons 8159d 15h /or1k/tags/nog_patch_58/or1ksim/cache/
626 store buffer added markom 8160d 04h /or1k/tags/nog_patch_58/or1ksim/cache/
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8181d 00h /or1k/tags/nog_patch_58/or1ksim/cache/
517 some performance optimizations markom 8185d 00h /or1k/tags/nog_patch_58/or1ksim/cache/
500 Added .cvsignore files for annoying generated files erez 8187d 03h /or1k/tags/nog_patch_58/or1ksim/cache/
429 cache configuration added markom 8208d 23h /or1k/tags/nog_patch_58/or1ksim/cache/
428 cache configuration added markom 8208d 23h /or1k/tags/nog_patch_58/or1ksim/cache/

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