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1447 This commit was manufactured by cvs2svn to create tag 'nog_patch_61'. 7097d 04h /or1k/tags/nog_patch_61/or1ksim/cache/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7097d 04h /or1k/tags/nog_patch_61/or1ksim/cache/
1406 Fix the declaration of `sec' in reg_ic_sec nogj 7097d 04h /or1k/tags/nog_patch_61/or1ksim/cache/
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7097d 04h /or1k/tags/nog_patch_61/or1ksim/cache/
1402 Do what dc_clock() did in mtspr() and remove it nogj 7097d 04h /or1k/tags/nog_patch_61/or1ksim/cache/
1386 Rework exception handling nogj 7103d 08h /or1k/tags/nog_patch_61/or1ksim/cache/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7112d 08h /or1k/tags/nog_patch_61/or1ksim/cache/
1376 aclocal && autoconf && automake phoenix 7131d 08h /or1k/tags/nog_patch_61/or1ksim/cache/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7137d 23h /or1k/tags/nog_patch_61/or1ksim/cache/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7147d 03h /or1k/tags/nog_patch_61/or1ksim/cache/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7160d 06h /or1k/tags/nog_patch_61/or1ksim/cache/
1308 Gyorgy Jeney: extensive cleanup phoenix 7351d 21h /or1k/tags/nog_patch_61/or1ksim/cache/
1249 Downgrading back to automake-1.4 lampret 7516d 21h /or1k/tags/nog_patch_61/or1ksim/cache/
1117 Ignore generated files for CVS purposes sfurman 7859d 21h /or1k/tags/nog_patch_61/or1ksim/cache/
1099 cvs bug fixed markom 7946d 09h /or1k/tags/nog_patch_61/or1ksim/cache/
1085 Bug fixed. simons 7958d 23h /or1k/tags/nog_patch_61/or1ksim/cache/
997 PRINTF should be used instead of printf; command redirection repaired markom 8048d 12h /or1k/tags/nog_patch_61/or1ksim/cache/
992 A bug when cache enabled and bus error comes fixed. simons 8050d 03h /or1k/tags/nog_patch_61/or1ksim/cache/
970 Testbench is now running on ORP architecture platform. simons 8055d 23h /or1k/tags/nog_patch_61/or1ksim/cache/
884 code cleaning - a lot of global variables moved to runtime struct markom 8092d 10h /or1k/tags/nog_patch_61/or1ksim/cache/
876 Beta release of ATA simulation rherveille 8099d 22h /or1k/tags/nog_patch_61/or1ksim/cache/
638 TLBTR CI bit is now working properly. simons 8250d 23h /or1k/tags/nog_patch_61/or1ksim/cache/
631 Real cache access is simulated now. simons 8253d 22h /or1k/tags/nog_patch_61/or1ksim/cache/
626 store buffer added markom 8254d 11h /or1k/tags/nog_patch_61/or1ksim/cache/
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8275d 07h /or1k/tags/nog_patch_61/or1ksim/cache/
517 some performance optimizations markom 8279d 06h /or1k/tags/nog_patch_61/or1ksim/cache/
500 Added .cvsignore files for annoying generated files erez 8281d 10h /or1k/tags/nog_patch_61/or1ksim/cache/
429 cache configuration added markom 8303d 06h /or1k/tags/nog_patch_61/or1ksim/cache/
428 cache configuration added markom 8303d 06h /or1k/tags/nog_patch_61/or1ksim/cache/
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8342d 10h /or1k/tags/nog_patch_61/or1ksim/cache/

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