OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_72/] - Rev 207

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
207 Several major changes to allow gdb to work with an Or1k implementation
that does not need a writeable PC. This version will use the breakpoint
vector and install a new vector into the EPC register, and then single
step out of the breakpoint exception. The breakpoint exception vector
must include only 2 commands: l.rfe and l.nop. Anything else and this
gdb version will fail w/ or1ksim.
chris 8322d 04h /or1k/tags/nog_patch_72/
206 Several modifications to support gdb in a new exception style mode.
This new version works with gdb, and does not require the simulator
to implement a writeable PC.
chris 8322d 04h /or1k/tags/nog_patch_72/
205 Adding debug capabilities. Half done. lampret 8326d 07h /or1k/tags/nog_patch_72/
204 Added function prototypes to stop gcc from complaining erez 8328d 23h /or1k/tags/nog_patch_72/
203 Updated from xess branch. lampret 8330d 12h /or1k/tags/nog_patch_72/
202 changed configure.in and acconfig.h to check for long long
reran autoheader & autoconf
erez 8335d 20h /or1k/tags/nog_patch_72/
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8335d 20h /or1k/tags/nog_patch_72/
200 Initial import simons 8339d 03h /or1k/tags/nog_patch_72/
199 Initial import simons 8339d 04h /or1k/tags/nog_patch_72/
198 Moved from testbench.old simons 8341d 15h /or1k/tags/nog_patch_72/
197 This is not used any more. simons 8341d 15h /or1k/tags/nog_patch_72/
196 Configuration SPRs added. simons 8341d 16h /or1k/tags/nog_patch_72/
195 New test added. simons 8341d 16h /or1k/tags/nog_patch_72/
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.
chris 8342d 00h /or1k/tags/nog_patch_72/
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.
chris 8342d 00h /or1k/tags/nog_patch_72/
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.
chris 8342d 09h /or1k/tags/nog_patch_72/
191 Added UART jitter var to sim config chris 8343d 05h /or1k/tags/nog_patch_72/
190 Added jitter initialization chris 8343d 05h /or1k/tags/nog_patch_72/
189 fixed mode handling for tick facility chris 8343d 06h /or1k/tags/nog_patch_72/
188 fixed PIC interrupt controller chris 8343d 06h /or1k/tags/nog_patch_72/
187 minor change to clear pending exception chris 8343d 06h /or1k/tags/nog_patch_72/
186 major change to UART structure chris 8343d 06h /or1k/tags/nog_patch_72/
185 major change to UART code chris 8343d 06h /or1k/tags/nog_patch_72/
184 modified decode for trace debugging chris 8343d 06h /or1k/tags/nog_patch_72/
183 changed special case for PICSR chris 8343d 06h /or1k/tags/nog_patch_72/
182 updated exception handling procedures chris 8343d 06h /or1k/tags/nog_patch_72/
181 Added trace/stall commands chris 8343d 06h /or1k/tags/nog_patch_72/
180 Updated debug. lampret 8343d 11h /or1k/tags/nog_patch_72/
179 Sim run script lampret 8363d 04h /or1k/tags/nog_patch_72/
178 Some test code lampret 8363d 04h /or1k/tags/nog_patch_72/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.