OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc1/] - Rev 74

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
74 Same as DMMU. lampret 8686d 23h /or1k/tags/rel-0-3-0-rc1/
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8686d 23h /or1k/tags/rel-0-3-0-rc1/
72 Added 'how to build GNU tools' lampret 8692d 00h /or1k/tags/rel-0-3-0-rc1/
71 Clean two typos. lampret 8697d 02h /or1k/tags/rel-0-3-0-rc1/
70 Basic setjmp/longjmp are ready. lampret 8697d 02h /or1k/tags/rel-0-3-0-rc1/
69 Sim debug. lampret 8698d 23h /or1k/tags/rel-0-3-0-rc1/
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8699d 00h /or1k/tags/rel-0-3-0-rc1/
67 Added simulator "application load". lampret 8699d 00h /or1k/tags/rel-0-3-0-rc1/
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.		 lampret 8699d 00h /or1k/tags/rel-0-3-0-rc1/
65 Added DMMU stats. lampret 8699d 00h /or1k/tags/rel-0-3-0-rc1/
64 SPR bit definition moved to spr_defs.h. lampret 8699d 00h /or1k/tags/rel-0-3-0-rc1/
63 Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry
alignment of bits).		 lampret 8699d 00h /or1k/tags/rel-0-3-0-rc1/
62 OR1K DMMU model. lampret 8699d 00h /or1k/tags/rel-0-3-0-rc1/
61 2000-09-26 Joel Sherrill <joel@OARcorp.com>

* libc/sys/rtems/include/pthread.h: Added file missed by earlier
commit of RTEMS modifications.		 joel 8713d 18h /or1k/tags/rel-0-3-0-rc1/
60 Memory model changed. lampret 8734d 03h /or1k/tags/rel-0-3-0-rc1/
59 2000-09-05 Joel Sherrill <joel@OARcorp.com>

* Merged newlib-1.8.2-rtems-20000905.diff which includes
or16 and or32 configuration support.		 joel 8734d 14h /or1k/tags/rel-0-3-0-rc1/
57 This commit was generated by cvs2svn to compensate for changes in r56, which
included commits to RCS files with non-trunk default branches.		 joel 8740d 12h /or1k/tags/rel-0-3-0-rc1/
55 Added 'dv' command for dumping memory as verilog model. lampret 8750d 00h /or1k/tags/rel-0-3-0-rc1/
54 Regular maintenance. lampret 8750d 00h /or1k/tags/rel-0-3-0-rc1/
53 Added setjmp/longjmp. lampret 8755d 00h /or1k/tags/rel-0-3-0-rc1/
52 Comment character changed. lampret 8810d 20h /or1k/tags/rel-0-3-0-rc1/
51 Exception detection changed a bit. lampret 8810d 20h /or1k/tags/rel-0-3-0-rc1/
50 Added CURINSN macro. lampret 8810d 20h /or1k/tags/rel-0-3-0-rc1/
49 Changed simulation mode to non-virtual (real). lampret 8810d 20h /or1k/tags/rel-0-3-0-rc1/
48 Added CCR. lampret 8810d 20h /or1k/tags/rel-0-3-0-rc1/
47 Added interrupt recognition and better memory dump. lampret 8810d 20h /or1k/tags/rel-0-3-0-rc1/
46 Added srand(). lampret 8810d 20h /or1k/tags/rel-0-3-0-rc1/
45 Added NONE. lampret 8810d 20h /or1k/tags/rel-0-3-0-rc1/
44 %s bug fixed. lampret 8816d 01h /or1k/tags/rel-0-3-0-rc1/
43 SUPV bit from SR is now saved into EPCR bit 0. lampret 8821d 04h /or1k/tags/rel-0-3-0-rc1/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.