OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc1/] [or1ksim/] [cache/] - Rev 1730

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1730 Avoid array lookups as far as possible. Precalculate as much as possible.
Increases performance when running with ic.		 nogj 6744d 15h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1649 Mark as many functions as possible static nogj 6746d 04h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1576 configure updates phoenix 6859d 01h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1557 Fix most warnings issued by gcc4 nogj 6882d 15h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1555 * Moved log2_int() from cuc/cuc.c as it is usefull for other things aswell.
* Changed code to use log2_int() instead of log2(), which is also a builtin
library function (fixes compile on gcc4).
* Moved is_power2() from sim-config.c to misc.c.		 nogj 6882d 15h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1506 * Remove very slow {set,test}sprbit{,s} functions.
* Remove uses of getsprbits in time critical functions.		 nogj 6949d 12h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.		 nogj 6992d 12h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7040d 08h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1406 Fix the declaration of `sec' in reg_ic_sec nogj 7040d 08h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7040d 08h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1402 Do what dc_clock() did in mtspr() and remove it nogj 7040d 08h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1386 Rework exception handling nogj 7046d 11h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7055d 12h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1376 aclocal && autoconf && automake phoenix 7074d 12h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7081d 03h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7090d 06h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7103d 10h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1308 Gyorgy Jeney: extensive cleanup phoenix 7295d 00h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1249 Downgrading back to automake-1.4 lampret 7460d 00h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1117 Ignore generated files for CVS purposes sfurman 7803d 01h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1099 cvs bug fixed markom 7889d 12h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
1085 Bug fixed. simons 7902d 02h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
997 PRINTF should be used instead of printf; command redirection repaired markom 7991d 15h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
992 A bug when cache enabled and bus error comes fixed. simons 7993d 06h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
970 Testbench is now running on ORP architecture platform. simons 7999d 02h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
884 code cleaning - a lot of global variables moved to runtime struct markom 8035d 13h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
876 Beta release of ATA simulation rherveille 8043d 01h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
638 TLBTR CI bit is now working properly. simons 8194d 03h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
631 Real cache access is simulated now. simons 8197d 01h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/
626 store buffer added markom 8197d 15h /or1k/tags/rel-0-3-0-rc1/or1ksim/cache/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.