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Log message |
Author |
Age |
Path |
1765 |
|
root |
5628d 12h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
1749 |
This commit was manufactured by cvs2svn to create tag 'rel-0-3-0-rc1'. |
|
5777d 17h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
1748 |
These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.
Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals. |
jeremybennett |
5777d 17h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
1745 |
These are the changes to allow or1ksim to build as a library as well as a standalone simulator. The concept of a "generic" peripheral is added, which will commuicate with an external model via upcalls. |
jeremybennett |
5813d 16h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
1743 |
Changes to bring behavior into line with the current OpenRISC 1000 specification and support GDB 6.8. A couple of small bugs with handling xterms and opening the remote debug channel are also fixed. Header files have been added to sources in Makefile.am files where they are missing, so that "make tags" will include them. Makefile.in files have been regenerated due to these changes. |
jeremybennett |
5814d 16h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
1576 |
configure updates |
phoenix |
6887d 11h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
1376 |
aclocal && autoconf && automake |
phoenix |
7102d 22h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
1249 |
Downgrading back to automake-1.4 |
lampret |
7488d 11h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
997 |
PRINTF should be used instead of printf; command redirection repaired |
markom |
8020d 02h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
879 |
Initial version of OpenRISC Custom Unit Compiler added |
markom |
8069d 18h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
538 |
memory width increased to 32bit; new memory test mem_test added - simple big endian test |
markom |
8247d 01h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
500 |
Added .cvsignore files for annoying generated files |
erez |
8253d 00h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
393 |
messages: exception on many places changed to abort |
markom |
8288d 03h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
247 |
Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support. |
jrydberg |
8318d 06h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
245 |
Initial revision |
cvs |
8318d 06h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
221 |
major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup |
markom |
8323d 00h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
123 |
Bugs fixed:
- l.rfe temporarly disables exceptions
- l.sys does PC -= 4
- breakpoints now supported at peripheria locations
- uart0.rt/.tx nonexistent file segment fault
Other modifications:
- replaced string names to instruction indexes
- execute.c executes specified (in ISA table) function
- modified ISA table - flag needed for gdb
- added or32.c, which supports or32.h
- added new instructions l.mac, l.msb, l.maci, l.macrc
and their executing functions (opcodes to be revisited)
- added header acconfig.h
- modified configuration files |
markom |
8456d 21h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
77 |
Regular update. |
lampret |
8682d 03h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
30 |
Updated SPRs, exceptions. Added 16450 device. |
lampret |
8828d 12h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
26 |
Clean up. |
lampret |
8859d 07h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
18 |
or16 added, or1k renamed to or32. |
lampret |
8862d 02h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
8 |
Initial revision. |
jrydberg |
8922d 19h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
6 |
Just a regular update with exception of cache simulation. MMU simulation still under development. |
lampret |
8923d 13h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |
3 |
This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches. |
cvs |
9049d 06h |
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/dlx/ |