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[/] [or1k/] [tags/] [rel-0-3-0-rc2/] - Rev 807

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Rev Log message Author Age Path
807 sched files moved to support dir markom 8157d 10h /or1k/tags/rel-0-3-0-rc2/
806 uart now partially uses scheduler markom 8157d 10h /or1k/tags/rel-0-3-0-rc2/
805 kbd, fb, vga devices now uses scheduler markom 8157d 11h /or1k/tags/rel-0-3-0-rc2/
804 memory regions can now overlap with MC -- not according to MC spec markom 8158d 04h /or1k/tags/rel-0-3-0-rc2/
803 Free irq handler fixed. simons 8160d 22h /or1k/tags/rel-0-3-0-rc2/
802 Cache and tick timer tests fixed. simons 8162d 09h /or1k/tags/rel-0-3-0-rc2/
801 l.muli instruction added markom 8164d 05h /or1k/tags/rel-0-3-0-rc2/
800 Bug fixed. simons 8165d 02h /or1k/tags/rel-0-3-0-rc2/
799 Wrapping around 512k boundary to simulate real hw. simons 8168d 20h /or1k/tags/rel-0-3-0-rc2/
798 Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary. simons 8168d 20h /or1k/tags/rel-0-3-0-rc2/
797 Changed hardcoded address for fake MC to use a define. lampret 8168d 21h /or1k/tags/rel-0-3-0-rc2/
796 Removed unused ports wb_clki and wb_rst_i lampret 8168d 21h /or1k/tags/rel-0-3-0-rc2/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8169d 01h /or1k/tags/rel-0-3-0-rc2/
794 Added again just recently removed full_case directive lampret 8169d 01h /or1k/tags/rel-0-3-0-rc2/
793 Added synthesis off/on for timescale.v included file. lampret 8169d 01h /or1k/tags/rel-0-3-0-rc2/
792 Fixed port names that changed. lampret 8169d 01h /or1k/tags/rel-0-3-0-rc2/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8169d 01h /or1k/tags/rel-0-3-0-rc2/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8169d 01h /or1k/tags/rel-0-3-0-rc2/
789 Added response from memory controller (addr 0x60000000) lampret 8169d 02h /or1k/tags/rel-0-3-0-rc2/
788 Some of the warnings fixed. lampret 8169d 02h /or1k/tags/rel-0-3-0-rc2/
787 Added romfs.tgz lampret 8169d 21h /or1k/tags/rel-0-3-0-rc2/
786 Moved UCF constraint file to the backend directory. lampret 8169d 21h /or1k/tags/rel-0-3-0-rc2/
785 Added XSV specific documentation. lampret 8169d 21h /or1k/tags/rel-0-3-0-rc2/
784 Added soem missing files. lampret 8169d 21h /or1k/tags/rel-0-3-0-rc2/
783 Added sim directory and sub files/dirs. lampret 8169d 21h /or1k/tags/rel-0-3-0-rc2/
782 Added the old SW directory. It needs to be updated for the new ORP environment and test cases moved to sw directory. lampret 8169d 21h /or1k/tags/rel-0-3-0-rc2/
781 Added design compiler scripts. However these are not ready for use yet .... They need to be updated for the ORP sources and ORP sources need to be updated as well. lampret 8169d 21h /or1k/tags/rel-0-3-0-rc2/
780 Added libraries. lampret 8169d 21h /or1k/tags/rel-0-3-0-rc2/
779 Added bench directory lampret 8169d 22h /or1k/tags/rel-0-3-0-rc2/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8169d 22h /or1k/tags/rel-0-3-0-rc2/

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