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[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [cpu/] - Rev 68

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68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8677d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
67 Added simulator "application load". lampret 8677d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.		 lampret 8677d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
65 Added DMMU stats. lampret 8677d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
64 SPR bit definition moved to spr_defs.h. lampret 8677d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
63 Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry
alignment of bits).		 lampret 8677d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
54 Regular maintenance. lampret 8728d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
52 Comment character changed. lampret 8789d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
51 Exception detection changed a bit. lampret 8789d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
50 Added CURINSN macro. lampret 8789d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
49 Changed simulation mode to non-virtual (real). lampret 8789d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
48 Added CCR. lampret 8789d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
47 Added interrupt recognition and better memory dump. lampret 8789d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
43 SUPV bit from SR is now saved into EPCR bit 0. lampret 8799d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
42 Bug fix. Only symbols with names shorter than 9 characters are loaded. lampret 8799d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
41 Bug fix. Now all COFF sections are loaded not just .text. lampret 8800d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
38 Virtual machine at the moment. lampret 8801d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
37 STACK_SIZE is not properly used (will be removed soon). lampret 8801d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
36 Fixed bug when loading "data" from .text segment (all insns are not only
decoded but also placed in simulator memory undecoded as data).		 lampret 8801d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
35 SLP hooks. lampret 8801d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
34 Started with SLP (not finished yet). lampret 8801d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
33 Handling of or1k exceptions. lampret 8805d 00h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
32 Interrupt recognition. lampret 8805d 00h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
30 Updated SPRs, exceptions. Added 16450 device. lampret 8805d 03h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
29 Adding OR16/OR32 insn decoder. lampret 8820d 00h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
28 Adding COFF loader. lampret 8820d 00h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
26 Clean up. lampret 8835d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
25 Bug fix in handling labels when loading code into simulator memory. lampret 8835d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
24 Static branch prediction added. lampret 8835d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/
23 Common OR1K backend for OR32 and OR16. lampret 8835d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/

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