| Rev |
Log message |
Author |
Age |
Path |
| 1765 |
|
root |
5602d 02h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1753 |
This commit was manufactured by cvs2svn to create tag 'rel-0-3-0-rc2'. |
|
5721d 09h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1751 |
These are the changes to support Or1ksim 0.3.0rc2. Most significantly they provide GDB RSP support. They also fix 5 outstanding bugs and satisfy one new feature request. |
jeremybennett |
5721d 11h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1748 |
These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.
Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals. |
jeremybennett |
5751d 07h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1747 |
Re-establishing this file cleanly. It is a link with the testbench, which
causes great hassle. It will have to be replaced. |
jeremybennett |
5787d 06h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1746 |
Bring the testbench SPR defs into line with the main code. This file really ought to go. |
jeremybennett |
5787d 06h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1745 |
These are the changes to allow or1ksim to build as a library as well as a standalone simulator. The concept of a "generic" peripheral is added, which will commuicate with an external model via upcalls. |
jeremybennett |
5787d 06h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1744 |
Changes to bring behavior into line with the current OpenRISC 1000 specification and support GDB 6.8. A couple of small bugs with handling xterms and opening the remote debug channel are also fixed. Header files have been added to sources in Makefile.am files where they are missing, so that "make tags" will include them. Makefile.in files have been regenerated due to these changes. |
jeremybennett |
5788d 06h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1743 |
Changes to bring behavior into line with the current OpenRISC 1000 specification and support GDB 6.8. A couple of small bugs with handling xterms and opening the remote debug channel are also fixed. Header files have been added to sources in Makefile.am files where they are missing, so that "make tags" will include them. Makefile.in files have been regenerated due to these changes. |
jeremybennett |
5788d 06h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1720 |
Warning/spelling/gramer/useless comment removal fixes. |
nogj |
6748d 03h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1715 |
Add the capability to the pic to simulate a level or edge triggered pic. Add
a clear_interrupt() function that the peripherals need to use to signal that
they negated their interrupt line. |
nogj |
6748d 04h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1692 |
Instead of playing games with the esp when a jump needs to be executed, use
longjmp() to get to the jump handling code. |
nogj |
6748d 04h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1686 |
Remove the immu_ex_from_insn hack. |
nogj |
6748d 04h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1678 |
Remove the ts_current hack by haveing the temporaries always shipped out before
any instruction that has the posibility to generate an exception |
nogj |
6748d 04h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1656 |
Pass the instruction operands as part of the op_queue structure. |
nogj |
6748d 05h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1652 |
Avoid division and multiplication as far as possible (they are slow) |
nogj |
6748d 05h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1585 |
added missing exception, fixes segfault with trap exception |
phoenix |
6839d 02h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1579 |
Add missing break; statements |
nogj |
6860d 13h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1576 |
configure updates |
phoenix |
6861d 02h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1557 |
Fix most warnings issued by gcc4 |
nogj |
6884d 16h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1555 |
* Moved log2_int() from cuc/cuc.c as it is usefull for other things aswell.
* Changed code to use log2_int() instead of log2(), which is also a builtin
library function (fixes compile on gcc4).
* Moved is_power2() from sim-config.c to misc.c. |
nogj |
6884d 16h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1551 |
Remove the pcprev global |
nogj |
6946d 05h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1550 |
* prototype() -> prototype(void) where appropriate.
* Use `static' where it can be used. |
nogj |
6946d 05h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1549 |
Spelling fixes |
nogj |
6946d 05h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1540 |
* Breakup the tick_job function into smaller ones.
* Fix lots of conner cases.
* Add tests for the tick timer. |
nogj |
6946d 05h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1532 |
Add pretty spr dumping code |
nogj |
6950d 04h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1531 |
Remove non-trigerable out-of-range checks |
nogj |
6950d 04h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1529 |
* The effective address as written to the I/DCBPR registers needs to be translated by the respective mmu.
* Don't treat any values as special in the handling of DCPBR, DCBFR, DCBIR, ICBPR and ICBIR. |
nogj |
6951d 07h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1525 |
Rename ADDR_PAGE to IADDR_PAGE |
nogj |
6951d 13h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
| 1513 |
Remove the flag global |
nogj |
6951d 13h |
/or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or1k/ |
