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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] - Rev 1780

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Rev Log message Author Age Path
1765 root 5587d 06h /or1k/tags/rel_1/or1200/rtl/verilog/
896 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8018d 06h /or1k/tags/rel_1/or1200/rtl/verilog/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8018d 06h /or1k/tags/rel_1/or1200/rtl/verilog/
871 Generic flip-flop based memory macro for register file. lampret 8054d 12h /or1k/tags/rel_1/or1200/rtl/verilog/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8054d 12h /or1k/tags/rel_1/or1200/rtl/verilog/
869 Added generic flip-flop based memory macro instantiation. lampret 8054d 12h /or1k/tags/rel_1/or1200/rtl/verilog/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8125d 12h /or1k/tags/rel_1/or1200/rtl/verilog/
794 Added again just recently removed full_case directive lampret 8125d 12h /or1k/tags/rel_1/or1200/rtl/verilog/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8125d 12h /or1k/tags/rel_1/or1200/rtl/verilog/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8125d 12h /or1k/tags/rel_1/or1200/rtl/verilog/
788 Some of the warnings fixed. lampret 8125d 13h /or1k/tags/rel_1/or1200/rtl/verilog/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8126d 09h /or1k/tags/rel_1/or1200/rtl/verilog/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8126d 10h /or1k/tags/rel_1/or1200/rtl/verilog/
776 Updated defines. lampret 8126d 10h /or1k/tags/rel_1/or1200/rtl/verilog/
775 Optimized cache controller FSM. lampret 8126d 10h /or1k/tags/rel_1/or1200/rtl/verilog/
774 Removed old files. lampret 8126d 10h /or1k/tags/rel_1/or1200/rtl/verilog/
737 Added alternative for critical path in DU. lampret 8141d 04h /or1k/tags/rel_1/or1200/rtl/verilog/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8144d 03h /or1k/tags/rel_1/or1200/rtl/verilog/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8144d 03h /or1k/tags/rel_1/or1200/rtl/verilog/
668 Lapsus fixed. simons 8168d 13h /or1k/tags/rel_1/or1200/rtl/verilog/
663 No longer using async rst as sync reset for the counter. lampret 8171d 03h /or1k/tags/rel_1/or1200/rtl/verilog/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8172d 00h /or1k/tags/rel_1/or1200/rtl/verilog/
636 Fixed combinational loops. lampret 8181d 09h /or1k/tags/rel_1/or1200/rtl/verilog/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8186d 04h /or1k/tags/rel_1/or1200/rtl/verilog/
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8190d 21h /or1k/tags/rel_1/or1200/rtl/verilog/
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8194d 15h /or1k/tags/rel_1/or1200/rtl/verilog/
596 SR[TEE] should be zero after reset. lampret 8194d 19h /or1k/tags/rel_1/or1200/rtl/verilog/
595 Fixed 'the NPC single-step fix'. lampret 8195d 14h /or1k/tags/rel_1/or1200/rtl/verilog/
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8195d 21h /or1k/tags/rel_1/or1200/rtl/verilog/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8198d 23h /or1k/tags/rel_1/or1200/rtl/verilog/

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