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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] - Rev 736

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Rev Log message Author Age Path
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8159d 16h /or1k/tags/rel_1/or1200/rtl/verilog/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8159d 16h /or1k/tags/rel_1/or1200/rtl/verilog/
668 Lapsus fixed. simons 8184d 01h /or1k/tags/rel_1/or1200/rtl/verilog/
663 No longer using async rst as sync reset for the counter. lampret 8186d 15h /or1k/tags/rel_1/or1200/rtl/verilog/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8187d 12h /or1k/tags/rel_1/or1200/rtl/verilog/
636 Fixed combinational loops. lampret 8196d 21h /or1k/tags/rel_1/or1200/rtl/verilog/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8201d 16h /or1k/tags/rel_1/or1200/rtl/verilog/
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8206d 09h /or1k/tags/rel_1/or1200/rtl/verilog/
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8210d 03h /or1k/tags/rel_1/or1200/rtl/verilog/
596 SR[TEE] should be zero after reset. lampret 8210d 08h /or1k/tags/rel_1/or1200/rtl/verilog/
595 Fixed 'the NPC single-step fix'. lampret 8211d 03h /or1k/tags/rel_1/or1200/rtl/verilog/
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8211d 09h /or1k/tags/rel_1/or1200/rtl/verilog/
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8214d 11h /or1k/tags/rel_1/or1200/rtl/verilog/
571 Changed alignment exception EPCR. Not tested yet. lampret 8214d 20h /or1k/tags/rel_1/or1200/rtl/verilog/
570 Fixed order of syscall and range exceptions. lampret 8214d 22h /or1k/tags/rel_1/or1200/rtl/verilog/
569 Default ASIC configuration does not sample WB inputs. lampret 8215d 07h /or1k/tags/rel_1/or1200/rtl/verilog/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8215d 11h /or1k/tags/rel_1/or1200/rtl/verilog/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8221d 16h /or1k/tags/rel_1/or1200/rtl/verilog/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8225d 20h /or1k/tags/rel_1/or1200/rtl/verilog/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8226d 09h /or1k/tags/rel_1/or1200/rtl/verilog/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8256d 12h /or1k/tags/rel_1/or1200/rtl/verilog/
401 *** empty log message *** simons 8259d 22h /or1k/tags/rel_1/or1200/rtl/verilog/
400 force_dslot_fetch does not work - allways zero. simons 8259d 22h /or1k/tags/rel_1/or1200/rtl/verilog/
399 Trap insn couses break after exits ex_insn. simons 8259d 22h /or1k/tags/rel_1/or1200/rtl/verilog/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8262d 18h /or1k/tags/rel_1/or1200/rtl/verilog/
390 Changed instantiation name of VS RAMs. lampret 8262d 20h /or1k/tags/rel_1/or1200/rtl/verilog/
387 Now FPGA and ASIC target are separate. lampret 8262d 21h /or1k/tags/rel_1/or1200/rtl/verilog/
386 Fixed VS RAM instantiation - again. lampret 8262d 21h /or1k/tags/rel_1/or1200/rtl/verilog/
370 Program counter divided to PPC and NPC. simons 8266d 19h /or1k/tags/rel_1/or1200/rtl/verilog/
367 Changed DSR/DRR behavior and exception detection. lampret 8267d 08h /or1k/tags/rel_1/or1200/rtl/verilog/

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