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[/] [or1k/] [tags/] [rel_10/] [or1200/] - Rev 958

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Rev Log message Author Age Path
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8008d 10h /or1k/tags/rel_10/or1200/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8010d 11h /or1k/tags/rel_10/or1200/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8010d 11h /or1k/tags/rel_10/or1200/
942 Delayed external access at page crossing. lampret 8010d 11h /or1k/tags/rel_10/or1200/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8022d 14h /or1k/tags/rel_10/or1200/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8038d 18h /or1k/tags/rel_10/or1200/
871 Generic flip-flop based memory macro for register file. lampret 8075d 00h /or1k/tags/rel_10/or1200/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8075d 00h /or1k/tags/rel_10/or1200/
869 Added generic flip-flop based memory macro instantiation. lampret 8075d 00h /or1k/tags/rel_10/or1200/
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8146d 00h /or1k/tags/rel_10/or1200/
794 Added again just recently removed full_case directive lampret 8146d 00h /or1k/tags/rel_10/or1200/
791 Fixed some ports in instnatiations that were removed from the modules lampret 8146d 00h /or1k/tags/rel_10/or1200/
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8146d 00h /or1k/tags/rel_10/or1200/
788 Some of the warnings fixed. lampret 8146d 01h /or1k/tags/rel_10/or1200/
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8146d 21h /or1k/tags/rel_10/or1200/
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8146d 21h /or1k/tags/rel_10/or1200/
776 Updated defines. lampret 8146d 21h /or1k/tags/rel_10/or1200/
775 Optimized cache controller FSM. lampret 8146d 21h /or1k/tags/rel_10/or1200/
774 Removed old files. lampret 8146d 22h /or1k/tags/rel_10/or1200/
737 Added alternative for critical path in DU. lampret 8161d 16h /or1k/tags/rel_10/or1200/
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8164d 15h /or1k/tags/rel_10/or1200/
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8164d 15h /or1k/tags/rel_10/or1200/
668 Lapsus fixed. simons 8189d 01h /or1k/tags/rel_10/or1200/
663 No longer using async rst as sync reset for the counter. lampret 8191d 15h /or1k/tags/rel_10/or1200/
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8192d 12h /or1k/tags/rel_10/or1200/
636 Fixed combinational loops. lampret 8201d 20h /or1k/tags/rel_10/or1200/
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8206d 15h /or1k/tags/rel_10/or1200/
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8211d 08h /or1k/tags/rel_10/or1200/
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8215d 02h /or1k/tags/rel_10/or1200/
596 SR[TEE] should be zero after reset. lampret 8215d 07h /or1k/tags/rel_10/or1200/

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