OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_12/] - Rev 217

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
217 Fixed some synthesis warnings. Configured with caches and MMUs. lampret 8332d 18h /or1k/tags/rel_12/
216 No longer needed. lampret 8338d 04h /or1k/tags/rel_12/
215 MP3 version. lampret 8338d 04h /or1k/tags/rel_12/
214 Removed redundant "long long" checks erez 8348d 06h /or1k/tags/rel_12/
213 Added test5 for DMA erez 8348d 07h /or1k/tags/rel_12/
212 Added DMA erez 8348d 07h /or1k/tags/rel_12/
211 Added check for "long long" erez 8348d 07h /or1k/tags/rel_12/
210 Updated debug. More cleanup. Added MAC. lampret 8351d 13h /or1k/tags/rel_12/
209 Update debug. lampret 8353d 18h /or1k/tags/rel_12/
208 Initial checkin with working port to or1k chris 8355d 05h /or1k/tags/rel_12/
207 Several major changes to allow gdb to work with an Or1k implementation
that does not need a writeable PC. This version will use the breakpoint
vector and install a new vector into the EPC register, and then single
step out of the breakpoint exception. The breakpoint exception vector
must include only 2 commands: l.rfe and l.nop. Anything else and this
gdb version will fail w/ or1ksim.		 chris 8355d 09h /or1k/tags/rel_12/
206 Several modifications to support gdb in a new exception style mode.
This new version works with gdb, and does not require the simulator
to implement a writeable PC.		 chris 8355d 09h /or1k/tags/rel_12/
205 Adding debug capabilities. Half done. lampret 8359d 13h /or1k/tags/rel_12/
204 Added function prototypes to stop gcc from complaining erez 8362d 04h /or1k/tags/rel_12/
203 Updated from xess branch. lampret 8363d 17h /or1k/tags/rel_12/
202 changed configure.in and acconfig.h to check for long long
reran autoheader & autoconf		 erez 8369d 01h /or1k/tags/rel_12/
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8369d 01h /or1k/tags/rel_12/
200 Initial import simons 8372d 08h /or1k/tags/rel_12/
199 Initial import simons 8372d 10h /or1k/tags/rel_12/
198 Moved from testbench.old simons 8374d 20h /or1k/tags/rel_12/
197 This is not used any more. simons 8374d 21h /or1k/tags/rel_12/
196 Configuration SPRs added. simons 8374d 21h /or1k/tags/rel_12/
195 New test added. simons 8374d 21h /or1k/tags/rel_12/
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.		 chris 8375d 05h /or1k/tags/rel_12/
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.		 chris 8375d 05h /or1k/tags/rel_12/
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.		 chris 8375d 14h /or1k/tags/rel_12/
191 Added UART jitter var to sim config chris 8376d 11h /or1k/tags/rel_12/
190 Added jitter initialization chris 8376d 11h /or1k/tags/rel_12/
189 fixed mode handling for tick facility chris 8376d 11h /or1k/tags/rel_12/
188 fixed PIC interrupt controller chris 8376d 11h /or1k/tags/rel_12/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.