OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] - Rev 1188

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1188 Added support for rams with byte write access. simons 7617d 13h /or1k/tags/rel_15/or1200/rtl/verilog/
1186 Added support for rams with byte write access. simons 7618d 12h /or1k/tags/rel_15/or1200/rtl/verilog/
1184 Scan signals mess fixed. simons 7625d 05h /or1k/tags/rel_15/or1200/rtl/verilog/
1179 BIST interface added for Artisan memory instances. simons 7633d 08h /or1k/tags/rel_15/or1200/rtl/verilog/
1161 When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. lampret 7699d 19h /or1k/tags/rel_15/or1200/rtl/verilog/
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7742d 22h /or1k/tags/rel_15/or1200/rtl/verilog/
1155 No functional change. Only added customization for exception vectors. lampret 7745d 23h /or1k/tags/rel_15/or1200/rtl/verilog/
1140 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs. lampret 7759d 01h /or1k/tags/rel_15/or1200/rtl/verilog/
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7759d 01h /or1k/tags/rel_15/or1200/rtl/verilog/
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7759d 20h /or1k/tags/rel_15/or1200/rtl/verilog/
1131 Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. lampret 7759d 20h /or1k/tags/rel_15/or1200/rtl/verilog/
1130 RFRAM type always need to be defined. lampret 7759d 20h /or1k/tags/rel_15/or1200/rtl/verilog/
1129 Added Altera LPM RAMs. Changed generic RAM output when OE inactive. lampret 7759d 21h /or1k/tags/rel_15/or1200/rtl/verilog/
1112 Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] lampret 7834d 18h /or1k/tags/rel_15/or1200/rtl/verilog/
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7879d 13h /or1k/tags/rel_15/or1200/rtl/verilog/
1083 SB mem width fixed. simons 7911d 08h /or1k/tags/rel_15/or1200/rtl/verilog/
1079 RAMs wrong connected to the BIST scan chain. mohor 7920d 05h /or1k/tags/rel_15/or1200/rtl/verilog/
1078 Previous check-in was done by mistake. mohor 7920d 07h /or1k/tags/rel_15/or1200/rtl/verilog/
1077 Signal scanb_sen renamed to scanb_en. mohor 7920d 07h /or1k/tags/rel_15/or1200/rtl/verilog/
1069 Signal scanb_eni renamed to scanb_en mohor 7924d 00h /or1k/tags/rel_15/or1200/rtl/verilog/
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7931d 02h /or1k/tags/rel_15/or1200/rtl/verilog/
1055 Removed obsolete comment. lampret 7962d 19h /or1k/tags/rel_15/or1200/rtl/verilog/
1054 Fixed a combinational loop. lampret 7962d 19h /or1k/tags/rel_15/or1200/rtl/verilog/
1053 Disabled cache inhibit atttribute. lampret 7962d 19h /or1k/tags/rel_15/or1200/rtl/verilog/
1038 Fixed a typo, reported by Taylor Su. lampret 7970d 02h /or1k/tags/rel_15/or1200/rtl/verilog/
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7970d 16h /or1k/tags/rel_15/or1200/rtl/verilog/
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7971d 03h /or1k/tags/rel_15/or1200/rtl/verilog/
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7971d 16h /or1k/tags/rel_15/or1200/rtl/verilog/
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 7974d 21h /or1k/tags/rel_15/or1200/rtl/verilog/
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7974d 23h /or1k/tags/rel_15/or1200/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.