OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_2/] [or1200/] [rtl/] - Rev 570

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
570 Fixed order of syscall and range exceptions. lampret 8214d 11h /or1k/tags/rel_2/or1200/rtl/
569 Default ASIC configuration does not sample WB inputs. lampret 8214d 20h /or1k/tags/rel_2/or1200/rtl/
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8215d 00h /or1k/tags/rel_2/or1200/rtl/
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8221d 05h /or1k/tags/rel_2/or1200/rtl/
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8225d 09h /or1k/tags/rel_2/or1200/rtl/
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8225d 22h /or1k/tags/rel_2/or1200/rtl/
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8256d 01h /or1k/tags/rel_2/or1200/rtl/
401 *** empty log message *** simons 8259d 11h /or1k/tags/rel_2/or1200/rtl/
400 force_dslot_fetch does not work - allways zero. simons 8259d 11h /or1k/tags/rel_2/or1200/rtl/
399 Trap insn couses break after exits ex_insn. simons 8259d 11h /or1k/tags/rel_2/or1200/rtl/
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8262d 07h /or1k/tags/rel_2/or1200/rtl/
390 Changed instantiation name of VS RAMs. lampret 8262d 09h /or1k/tags/rel_2/or1200/rtl/
387 Now FPGA and ASIC target are separate. lampret 8262d 10h /or1k/tags/rel_2/or1200/rtl/
386 Fixed VS RAM instantiation - again. lampret 8262d 10h /or1k/tags/rel_2/or1200/rtl/
370 Program counter divided to PPC and NPC. simons 8266d 08h /or1k/tags/rel_2/or1200/rtl/
367 Changed DSR/DRR behavior and exception detection. lampret 8266d 21h /or1k/tags/rel_2/or1200/rtl/
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8267d 16h /or1k/tags/rel_2/or1200/rtl/
360 Added OR1200_REGISTERED_INPUTS. lampret 8269d 09h /or1k/tags/rel_2/or1200/rtl/
359 Added optional sampling of inputs. lampret 8269d 09h /or1k/tags/rel_2/or1200/rtl/
358 Fixed virtual silicon single-port rams instantiation. lampret 8269d 09h /or1k/tags/rel_2/or1200/rtl/
357 Fixed dbg_is_o assignment width. lampret 8269d 09h /or1k/tags/rel_2/or1200/rtl/
356 Break point bug fixed simons 8269d 11h /or1k/tags/rel_2/or1200/rtl/
354 Fixed width of du_except. lampret 8270d 05h /or1k/tags/rel_2/or1200/rtl/
353 Cashes disabled. simons 8270d 16h /or1k/tags/rel_2/or1200/rtl/
352 OR1200_REGISTERED_OUTPUTS can now be enabled. lampret 8271d 19h /or1k/tags/rel_2/or1200/rtl/
351 Fixed some l.trap typos. lampret 8271d 20h /or1k/tags/rel_2/or1200/rtl/
350 For GDB changed single stepping and disabled trap exception. lampret 8271d 21h /or1k/tags/rel_2/or1200/rtl/
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8276d 20h /or1k/tags/rel_2/or1200/rtl/
337 Fixed tick timer interrupt reporting by using TTCR[IP] bit. lampret 8276d 20h /or1k/tags/rel_2/or1200/rtl/
328 Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. lampret 8278d 04h /or1k/tags/rel_2/or1200/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.